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AS7C33512NTD32A-166BI

Description
ZBT SRAM, 512KX32, 8.5ns, CMOS, PBGA165, BGA-165
Categorystorage    storage   
File Size447KB,22 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C33512NTD32A-166BI Overview

ZBT SRAM, 512KX32, 8.5ns, CMOS, PBGA165, BGA-165

AS7C33512NTD32A-166BI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeBGA
package instructionTBGA, BGA165,11X15,40
Contacts165
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time8.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density16777216 bit
Memory IC TypeZBT SRAM
memory width32
Number of functions1
Number of terminals165
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.04 A
Minimum standby current3.14 V
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width13 mm
Base Number Matches1
April 2004
®
AS7C33512NTD32A
AS7C33512NTD36A
3.3V 512K × 32/36 SRAM with NTD
TM
Features
Organization: 524,288 words × 32 or 36 bits
NTD
™1
architecture for efficient bus operation
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.4/3.8 ns
Fast OE access time: 3.4/3.8 ns
Fully synchronous operation
Flow-through or pipelined mode
1. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trade-
marks mentioned in this document are the property of their respective owners.
Asynchronous output enable control
Available in 100-pin TQFP and 165-ball BGA package
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[18:0]
19
D
Address
register
Burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
FT
LBO
ZZ
32/36
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
512K x 32/36
SRAM
Array
DQ[a,b,c,d]
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.4
300
90
40
-133
7.5
133
3.8
275
80
40
Units
ns
MHz
ns
mA
mA
mA
4/30/04, v 2.5
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
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