THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
DS3006 - 2.1
ZN427E8 / ZN427J8
MICROPROCESSOR COMPATIBLE
8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER
The ZN427 is an 8-bit successive approximation converter
with three-state outputs to permit easy interfacing to a
common data bus. The IC contains a voltage switching DAC,
a fast comparator, successive approximation logic and a
2.56V precision bandgap reference, the use of which is pin
optional to retain flexibility. An external fixed or varying
reference may therefore be substituted, thus allowing
ratiometic operation
Only passive external components are required for
operation of the converter.
BUSY (END OF CONVERSION)
RD (OUTPUT ENABLE)
CLOCK
WR (START CONVERSION)
R
EXT
V
IN
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
+V
CC
(+5V)
FEATURES
s
s
s
s
s
s
s
s
s
Easy Interfacing to Microprocessor, or Operates as a
'Stand-Alone' Converter
Fast: 10 microseconds Conversion time Guaranteed
No Missing Codes over Operating Temperature Range
Data Outputs Three-State TTL Compatible, other
Logic Inputs and Output TTL and CMOS Compatible
Choice of On-Chip or External Reference Voltage
Ratiometric Operation
Unipolar or Bipolar Input Ranges
Complementary to ZN428 DAC
Commercial or Military Temperature Range
V
REF
IN
V
REF
OUT
GROUND
ZN427J8 (DC18)
ZN427E8 (DP18)
Fig.1 Pin connection - top view
ORDERING INFORMATION
Device type
ZN427E8
ZN427J8
Operating temperature
0°C to +70°C
-55°C to +125°C
Package
DP18
DC18
8
VREF OUT
D TO A OUTPUT
R-2R LADDER
COMPARATOR
-
VIN
REXT
CLOCK
INPUT
6
5
4
3
SUCCESSIVE
APPROXIMATION REGISTER
WR (START CONVERSION)
1
BUSY (END CONVERSION)
ANALOGUE VOLTAGE SWITCHES
+
9
GROUND
7
VREF IN
+2.5V
REFERENCE
VCC
(+5V)
10
3-STATE BUFFERS
2
RD (OUTPUT ENABLE)
11
MSB
12
13
14
15
16
17
18
LSB
Fig.2 System diagram
ZN427
ABSOLUTE MAXIMUM RATINGS
Supply voltage V
CC
Max. voltage, logic and V
REF
input
Operating temperature range
Storage temperature range
+7.0V
+V
CC
0°C to +70°C (ZN427E8)
-55°C to +125°C (ZN427J8)
-55°C to +125°C
ELECTRICAL CHARACTERISTICS
(at V
CC
= 5V, T
amb
= 25°C unless otherwise specified).
Parameter
Converter
Resolution
Linearity error
Differential non-linearity
Linearity error T.C.
Differential non-linearity T.C.
Full-scale (gain) T.C.
Zero T.C.
Zero transition
00000000
to 00000001
F.S. transition
11111110
to 11111111
Conversion time
External reference voltage
Supply voltage (V
CC
)
Supply current
Power consumption
Comparator
Input current
Input resistance
Tail current, I
EXT
Negative supply, V–
Input voltage
Internal voltagee reference
Output voltage
Slope resistance
V
REF
temperature coefficient
Reference current
Logic
(over operating temperature range)
High level input voltage V
IH
Low level input voltage V
IL
High level input current,
WR
and RD inputs I
IH
High level input current,
Clock input I
IH
Low level input current I
IL
High level output current I
OH
Low level output current I
OL
High level output voltage V
OH
Low level output voltage V
OL
Disable output leakage
Input clamp diode voltage
Read input to data output
Enable/disable delay time t
RD
Start pulse width tWR
WR
to
BUSY
propagation delay t
BD
Clock pulse width
Maximum clock frequency
Min.
Typ.
Max.
Units
Bits
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
µV/°C
mV
mV
V
µs
V
V
mA
mW
µA
kΩ
µA
V
V
Conditions
8
-
-
-
-
-
-
12
10
2.545
-
1.5
4.5
-
-
-
-
±0.5
±3
±6
±2.5
±8
15
13
2.550
-
-
-
25
125
-
±0.5
-
-
-
-
-
18
16
2.555
10
3.0
5.5
40
-
External Ref. 2.5V
DC Package
DP Package
V
REF IN
= 2.560V
See note 1
-
-
25
-3.0
-0.5
1
100
-
-
-
-
-
15
-30.0
3.5
V
IN
= +3V, R
EXT
= 82kΩ
V - = -5V
See comparator (page x-xx)
2.475
-
-
4
2.560
0.5
50
-
2.625
2
-
15
V
Ω
ppm/°C
mA
R
REF
= 390Ω, C
REF
= 4µ7
See reference (page x-xx)
2.0
-
-
-
-
-
-
-
-
2.4
-
-
-
-
-
250
-
500
900
-
-
-
-
-
-
-
-
-
-
-
-
-
-
180
160
-
-
1000
-
0.8
50
15
100
30
-5
-100
1.6
-
0.4
2
-1.5
250
250
-
250
-
-
V
V
µA
µA
µA
µA
µA
µA
mA
V
V
µA
V
ns
ns
ns
ns
ns
kHz
V
IN
= 5.5V, V
CC
= max.
V
IN
= 2.4V, V
CC
= max.
V
IN
= 5.5V, V
CC
= max.
V
IN
= 2.4V, V
CC
= max.
V
IN
= 0.4V, V
CC
= max.
I
OH
= max., V
CC
= min.
I
OL
= max., V
CC
= min.
V
O
= 2.4V
See Fig.9
See Fig.9
See note 1
Note 1:
A 900kHz clock gives a conversion time of 10µs (9 clock periods).
2
ZN427
GENERAL CIRCUIT OPERATION
The ZN427 utilises the successive approximation technique.
Upon receipt of a negative-going pulse at the
WR
input the
BUSY
output goes low, the MSB is set to 1 and all other bits
are set to 0, which produces an output voltage of V
REF/2
from the
DAC. This is compared to the input voltage V
IN
; a decision is
made on the next negative clock edge to reset the
MSB to 0 if
V
REF
V
REF
> V
IN
or leave it set to 1 if
< V
IN
.
2
2
to 1. This procedure is repeated for all eight bits. On the ninth
negative clock edge
BUSY
goes high indicating that the
conversion is complete.
During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking
RD
high, thus enabling the
three-state output. Readout is non-destructive. The
BUSY
output may be tied to the RD input to automatically enable the
outputs when the data is valid.
For reliable operation of the converter the start pulse applied
to the
WR
input must meet certain timing criteria with respect
to the converter clock. These are detailed in the timing
diagram of Fig.3.
Bit 2 is set to 1 on the same clock edge, producing an output
V
REF
V
REF
V
REF
from the DAC of
or
+
depending on the state
4
2
4
of the MSB. This voltage is compared to V
IN
and on the next
clock edge a decision is made regarding bit 2, whilst bit 3 is set
Fig.3 Timing diagram
NOTES ON TIMING DIAGRAM
1. A conversion sequence is shown for the digital word
01100110. For clarity the three-state outputs are shown as
being enabled during the conversion, but normal practice
would be to disable them until the conversion was complete.
2. The
BUSY
output goes low during a conversion. When
BUSY
goes high at the end of a conversion the output data is
valid. In a microprocessor system the
BUSY
output can be
used to generate an interrupt request when the conversion is
complete.
3
ZN427
3. In the timing diagram cross hatching indicates a 'don't
care' condition.
4. The start pulse operates as an asynchronous
(independent of clock) reset that sets the MSB output to 1 and
sets all other outputs and the end of conversion flag to 0. This
resetting occurs on the low-going edge of the start pulse and
as long as
WR
is low the converter is inhibited. Conversion
commences on the first active (negative going) clock edge
after the
WR
input has gone high again, when the MSB
decision is made. A number of timing constraints thus supply
to the start pulse.
(a) The minimum duration of the start pulse is 250ns, to allow
reliable resetting of the converter logic circuits.
(b) There is no limit to the maximum duration of the start pulse.
(c) To allow the MSB to settle at least 1.5µs must elapse
between the negative going edge of the start pulse and the first
active clock edge that indicates the MSB desicion.
(d) To ensure relaible clocking the positive-going edge of the
start pulse should not occur within 200ns of an active
(negative-going) clock edge. The ideal place for the positive-
going edge of the start pulse is coincident with a positive-going
clock edge. As a special case of the above conditions that
start pulse may be synchronous with a negative-going clock
pulse.
PRACTICAL CLOCK AND SYNCHRONISING
CIRCUITS
The actual method of generating the clock signal and
synchronising it to the start conversion system in which the
ZN427 is incorporated.
When used with a microprocessor the ZN427 can be treated
as RAM and can be assigned a memory address using an
address decoder. If the
µP
clock is used to drive the ZN427
and the
µP
write pulse meets the ZN427 timing criteria with
respect to the
µP
clock then generating the start pulse is
simply a matter of gating the decoded address with the
microprocessor write pulse. Whilst the conversion is being
performed the microprocesor can perform other instructions
or No operation (NOP). when the conversion is complete the
outputs can be enabled onto the bus by gating the decoded
address with the read pulse. A timing diagram for this
sequence of operation is given in Fig.4.
An advantage of using the microprocessor clock is that the
conversion time is known precisely in terms of machine
cycles. the data outputs may therefore be read after a fixed
delay of at least nine clock cycles after the end of the
WR
pulse, when the conversion will be complete.
Alternatively the read operation may be initiated by using the
BUSY
output to generate interrupt request.
Fig.4 Typical timing diagram using
µ
P clock and write pulse
In some systems, for example single-chip microcomputers
such as the 8048, this simple method may not be feasible for
one or more of the following reasons:
(a) The MPU clock is not available externally.
(b) The clock frequency is too high.
4
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