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P4C1256L-70L32CLF

Description
Standard SRAM, 32KX8, 70ns, CMOS, 0.450 X 0.550 INCH, ROHS COMPLIANT, LCC-32
Categorystorage    storage   
File Size833KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Environmental Compliance
Download Datasheet Parametric View All

P4C1256L-70L32CLF Overview

Standard SRAM, 32KX8, 70ns, CMOS, 0.450 X 0.550 INCH, ROHS COMPLIANT, LCC-32

P4C1256L-70L32CLF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPyramid Semiconductor Corporation
Parts packaging codeQFJ
package instructionQCCN,
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time70 ns
JESD-30 codeR-XQCC-N32
length13.97 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialUNSPECIFIED
encapsulated codeQCCN
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.905 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.43 mm
Base Number Matches1
P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70/85
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
— 28-Pin 600 mil DIP
— 28-Pin 300 mil CERDIP
— 28-Pin 300 mil Narrow Body SOP
— 28-Pin LCC (350x550mil)
— 32-Pin LCC (450x550mil)
DESCRIPTION
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
The P4C1256L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
FUNCTIONAL BLOCk DIAgRAM
PIN CONFIgURATIONS
DIP (P6, D5-2), SOP (S11-3)
TOP VIEW
LCC PIN CONFIGURATIONS AT END OF DATASHEET
Document #
SRAM121
REV F
Revised September 2010
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