enables a blend of power conversion performance and
power management features.
The ZL6100 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 3.3V input to a
multi-phase supply operating from a 12V input. The ZL6100
eliminates the need for complicated power supply managers
as well as numerous external discrete components.
All operating features can be configured by simple
pin-strap/resistor selection or through the SMBus™ serial
interface. The ZL6100 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for communication between other Zilker Labs devices.
Features
Power Conversion
• Efficient Synchronous Buck Controller
• Adaptive Light Load Efficiency Optimization
• 3V to 14V Input Range
• 0.54V to 5.5V Output Range (with Margin)
• ±1% Output Voltage Accuracy
• Internal 3 A MOSFET Drivers
• Fast Load Transient Response
• Current Sharing and Phase Interleaving
•
Snapshot™
Parameter Capture
• 36 Ld 6mmx6mm QFN Package
• Pb-Free (RoHS Compliant)
Power Management
• Digital Soft-start/stop
• Precision Delay and Ramp-up
• Power-Good/Enable
• Voltage Tracking, Sequencing and Margining
Ordering Information
PART
NUMBER
(Note)
ZL6100ALAF*
PART
MARKING
6100
TEMP.
RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
PKG.
DWG. #
• Voltage/Current/Temperature Monitoring
• I
2
C/SMBus Interface (PMBus Compatible)
• Output Voltage and Current Protection
• Internal Non-volatile Memory (NVM)
36 Ld QFN L36.6x6A
*Add “T” or “TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
EN PG DLY
FC
Applications
• Servers/Storage Equipment
• Telecom/Datacom Equipment
• Power Supplies (Memory, DSP, ASIC, FPGA)
ILIM CFG UVLO V25 VR VDD
V
SS
VTRK
MGN
SYNC
DDC
NON-
VOLATILE
MEMORY
SCL
SDA
SALRT
LDO
POWER
MANAGEMENT
DRIVER
BST
GH
SW
GL
VSEN+
VSEN-
ISENA
ISENB
PWM
CONTROLLER
CURRENT
SENSE
TEMP
SENSOR
I
2
C
MONITOR
ADC
SA
XTEMP
PGND SGND DGND
FIGURE 1. BLOCK DIAGRAM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
ZL6100
Table of Contents
Features ............................................................................................................................................................................................. 1
Power Conversion ......................................................................................................................................................................... 1
Power Management....................................................................................................................................................................... 1
Absolute Maximum Ratings............................................................................................................................................................... 3
Power Conversion Overview ......................................................................................................................................................... 9
Power Management Overview..................................................................................................................................................... 10
Output Voltage Selection ............................................................................................................................................................. 11
Switching Frequency and PLL ..................................................................................................................................................... 15
Power Train Component Selection .............................................................................................................................................. 16
Current Limit Threshold Selection ............................................................................................................................................... 19
Adaptive Frequency Control ........................................................................................................................................................ 23
Power Management Functional Description.................................................................................................................................................. 24
Voltage Tracking.......................................................................................................................................................................... 26
Voltage Margining ........................................................................................................................................................................ 26
Digital-DC Bus ............................................................................................................................................................................. 28
Temperature Monitoring Using the XTEMP Pin........................................................................................................................... 29
Active Current Sharing................................................................................................................................................................. 29
Non-Volatile Memory and Device Security Features ................................................................................................................... 32
Related Tools and Documentation .................................................................................................................................................. 32
Related Documentation................................................................................................................................................................... 32
Revision History .............................................................................................................................................................................. 32
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Voltage measured with respect to SGND.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
3. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Includes margin limits.
Electrical Specifications
PARAMETER
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C. Temperature
limits established by characterization and are not production tested.
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT AND SUPPLY CHARACTERISTICS
I
DD
Supply Current at f
SW
= 200kHz
I
DD
Supply Current at f
SW
= 1.4MHz
I
DDS
Shutdown Current
VR Reference Output Voltage
V25 Reference Output Voltage
OUTPUT CHARACTERISTICS
Output Voltage Adjustment range (Note 5)
Output Voltage Set-point Resolution (Note 6)
V
IN
> V
OUT
Set using resistors
Set using I
2
C/SMBus
Output Voltage Accuracy (Note 7)
VSEN input Bias Current
Current Sense Differential Input
Voltage (Ground Referenced)
Includes line, load, temp
VSEN = 5.5V
V
ISENA
- V
ISENB
0.6
–
–
-1
–
-100
- 50
-100
-1
-100
2
0.002
–
10
±0.025
–
110
–
–
–
–
–
–
–
5.0
–
–
1
200
100
50
100
1
100
200
500
V
mV
% FS
(Note 6)
%
µA
mV
mV
µA
µA
µA
ms
s
GH, GL no load;
MISC_CONFIG[7] = 1
EN = 0V
No I
2
C/SMBus activity
V
DD
> 6V, I
VR
< 20mA
V
R
> 3V, I
V25
< 20mA
–
–
–
4.5
2.25
16
25
6.5
5.2
2.5
30
50
9
5.5
2.75
mA
mA
mA
V
V
Current Sense Differential Input Voltage
V
ISENA
- V
ISENB
(V
OUT
Referenced; V
OUT
must be less than 4.0V)
Current Sense Input Bias Current
Current Sense Input Bias Current
(V
OUT
Referenced, V
OUT
< 4.0 V)
Soft-start Delay Duration Range (Note 8)
Ground referenced
ISENA
ISENB
Set using DLY pin or resistor
Set using I
2
C/SMBus
3
FN6876.1
September 8, 2009
ZL6100
Electrical Specifications
PARAMETER
Soft-start Delay Duration Accuracy
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
CONDITIONS
Turn-on delay (precise mode) (Notes 8, 9)
Turn-on delay (normal mode) (Note 10)
Turn-off delay (Note 10)
Soft-start Ramp Duration Range
Set using SS pin or resistor
Set using I
2
C pin
Soft-start Ramp Duration Accuracy
LOGIC INPUT/OUTPUT CHARACTERISTICS
Logic Input Leakage Current
Logic Input Low, V
IL
Logic Input OPEN (N/C)
Logic Input high, V
IH
Logic Output Low, V
OL
Logic Output High, V
OH
I
OL
≤
4mA (Note 15)
I
OH
≥
-2mA (Note 15)
Multi-mode logic pins
Push-Pull Logic pins
-250
–
–
2.0
–
2.25
–
–
1.4
–
–
–
250
0.8
–
–
0.4
–
nA
V
V
V
V
V
MIN
–
–
–
0
0
–
TYP
±0.25
-1/+5
-1/+5
–
–
100
MAX
–
–
–
200
200
–
UNIT
ms
ms
ms
ms
ms
µs
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-point Accuracy
Maximum PWM Duty Cycle
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
GATE DRIVERS
High-side Driver Voltage
High-side Driver Peak Gate Drive Current
(Pull-down)
High-side Driver Pull-up Resistance
High-side Driver Pull-down Resistance
Low-side Driver Peak Gate Drive Current
(Pull-up)
Low-side Driver Peak Gate Drive
Current (pull-down)
Low-side Driver Pull-up Resistance
Low-side Driver Pull-down Resistance
SWITCHING TIME
GH Rise and Fall time
GL Rise and Fall time
TRACKING
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy
VTRK Regulation Accuracy
FAULT PROTECTION CHARACTERISTICS
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
Factory default
Configurable via I
2
C/SMBus
Configurable via I
2
C/SMBus
2.85
-150
–
0
–
–
3
–
16
150
–
100
V
mV
%
%
VTRK = 5.5V
100% Tracking, V
OUT
- VTRK
100% Tracking, V
OUT
- VTRK
–
-100
-1
110
–
–
200
+100
1
µA
mV
%
(V
BST
- V
SW
) = 4.5V, C
LOAD
= 2.2nF (Note 14)
V
R
= 5V, C
LOAD
= 2.2nF (Note 14)
–
–
5
5
20
20
ns
ns
(V
BST
- V
SW
)
(V
BST
- V
SW
) = 4.5V (Note 14)
(V
BST
- V
SW
) = 4.5V, (V
BST
- V
GH
) = 50mV (Note 14)
(V
BST
- V
SW
) = 4.5V, (V
GH
- V
SW
) = 50mV (Note 14)
V
R
= 5V
V
R
= 5V
V
R
= 5V, (V
R
- V
GL
) = 50mV (Note 14)
V
R
= 5V, (V
GL
- PGND) = 50mV (Note 14)
–
2
–
–
–
–
–
–
4.5
3
0.8
0.5
2.5
1.8
1.2
0.5
–
–
2
2
–
–
2
2
V
A
Ω
Ω
A
A
Ω
Ω
Predefined settings (see Table 12)
Factory default
(Note 14)
External clock source
200
-5
95
150
-13
–
–
–
–
–
1400
5
–
–
13
kHz
%
%
ns
%
4
FN6876.1
September 8, 2009
ZL6100
Electrical Specifications
PARAMETER
UVLO Delay
Power-Good V
OUT
Threshold
Power-Good V
OUT
Hysteresis
Power-Good Delay
(Note 14)
Factory default
Factory default
Using pin-strap or resistor (Note 11)
Configurable via I
2
C/SMBus (Note 14)
VSEN Undervoltage Threshold
Factory default
Configurable via I
2
C/SMBus (Note 14)
VSEN Overvoltage Threshold
Factory default
Configurable via I
2
C/SMBus (Note 14)
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault
Response Time
Current Limit Set-point Accuracy
(V
OUT
Referenced)
Current Limit Set-point Accuracy
(Ground referenced)
Current Limit Protection Delay
Factory default
Configurable via I
2
C/SMBus (Note 14)
Temperature Compensation of
Current Limit Protection Threshold
Thermal Protection Threshold
(Junction Temperature)
Thermal Protection Hysteresis
NOTES:
5. Does not include margin limits.
6. Percentage of Full Scale (FS) with temperature compensation applied.
7. V
OUT
measured at the termination of the VSEN+ and VSEN- sense points.
8. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approx 2ms, where in normal mode it may vary up to 4ms.
9. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
10. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
11. Factory default Power-Good delay is set to the same value as the soft-start ramp time.
12. Percentage of Full Scale (FS) with temperature compensation applied.
13. t
SW
= 1/f
SW
, where f
SW
is the switching frequency.
14. Limits established by characterization and not production tested.
15. Normal capacitance of logic pins is 5pF.
Factory default
Configurable via I
2
C/SMBus (Note 14)
Factory default
Configurable via I
2
C/SMBus (Note 14)
Factory default
Configurable via I
2
C/SMBus (Note 14)
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
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