ZL2106
Data Sheet
February 19, 2009
FN6852.0
6A Digital-DC Synchronous Step-Down DC-DC Converter
Description
The ZL2106 is an innovative power conversion and
management IC that combines an integrated
synchronous step-down DC-DC converter with key
power management functions in a small package,
resulting in a flexible and integrated solution.
Zilker Labs Digital-DC™ technology enables
unparalleled power management integration while
delivering industry-leading performance in a tiny
footprint.
The ZL2106 can provide an output voltage from
0.54 V to 5.5 V (with margin) from an input
voltage between 4.5 V and 14 V. Internal low
R
DS(ON)
synchronous power MOSFETs enable the
ZL2106 to deliver continuous loads up to 6 A with
high efficiency. An internal Schottky bootstrap
diode reduces discrete component count. The
ZL2106 also supports phase spreading to reduce
system input capacitance.
Power management features such as digital soft-
start delay and ramp, sequencing, tracking, and
margining can be configured by simple pin-
strapping or through an on-chip serial port. The
ZL2106 uses the PMBus™ protocol for
communication with a host controller and the
Digital-DC bus for interoperability between other
Zilker Labs devices.
Features
Power Conversion
Efficient synchronous buck controller
Integrated MOSFET switches
6 A continuous output current
4.5 V to 14 V input range
0.54 V to 5.5 V output range (with margin)
±1% output voltage accuracy
200 kHz to 1 MHz switching frequency
Phase spreading and Fault spreading
Snapshot™
parametric capture
Small footprint QFN package (6 x 6 mm)
Power Management
Digital soft start/stop
Precision delay and ramp-up
Power good/enable
Voltage tracking, sequencing, and margining
Voltage / current / temperature monitoring
Output voltage and current protection
I
2
C/SMBus interface, PMBus compatible
Internal non-volatile memory (NVM)
Applications
Telecom, Networking, Storage equipment
High-density servers
Test & Measurement equipment
Industrial control equipment
5V & 12V distributed power systems
Figure 1. Block Diagram
1
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ZL2106
Table of Contents
1. Electrical Characteristics ...............................................................................................................................................3
2. Typical Performance Curves .........................................................................................................................................6
3. Pin Descriptions ............................................................................................................................................................8
4. Typical Application Circuit.........................................................................................................................................10
5. ZL2106 Overview .......................................................................................................................................................11
5.1 Digital-DC Architecture........................................................................................................................................11
5.2 Power Conversion Overview ................................................................................................................................11
5.3 Power Management Overview..............................................................................................................................13
5.4 Multi-mode Pins....................................................................................................................................................13
6. Power Conversion Functional Description..................................................................................................................15
6.1 Internal Bias Regulators and Input Supply Connections ......................................................................................15
6.2 High-side Driver Boost Circuit .............................................................................................................................15
6.3 Output Voltage Selection ......................................................................................................................................15
6.4 Start-up Procedure.................................................................................................................................................16
6.5 Soft Start Delay and Ramp Times.........................................................................................................................16
6.6 Power Good (PG)..................................................................................................................................................18
6.7 Switching Frequency and PLL..............................................................................................................................18
6.8 Component Selection ............................................................................................................................................19
6.9 Current Sensing and Current Limit Threshold Selection ......................................................................................22
6.10 Loop Compensation ............................................................................................................................................23
6.11 Driver Dead-time Control ...................................................................................................................................23
7. Power Management Functional Description ...............................................................................................................24
7.1 Input Undervoltage Lockout .................................................................................................................................24
7.2 Output Overvoltage Protection .............................................................................................................................24
7.3 Output Pre-Bias Protection ...................................................................................................................................24
7.4 Output Overcurrent Protection..............................................................................................................................25
7.5 Thermal Overload Protection................................................................................................................................25
7.6 Voltage Tracking...................................................................................................................................................26
7.7 Voltage Margining ................................................................................................................................................27
7.8 I
2
C/SMBus Communications ................................................................................................................................28
7.9 I
2
C/SMBus Device Address Selection ..................................................................................................................28
7.10 Digital-DC Bus ...................................................................................................................................................28
7.11 Phase Spreading ..................................................................................................................................................29
7.12 Output Sequencing..............................................................................................................................................29
7.13 Fault Spreading ...................................................................................................................................................30
7.14 Monitoring via I
2
C/SMBus .................................................................................................................................30
7.15
Snapshot™
Parametric Capture ..........................................................................................................................30
7.16 Non-Volatile Memory and Device Security Features .........................................................................................31
8. Package Dimensions....................................................................................................................................................32
9. Ordering Information ..................................................................................................................................................33
10. Tools and Related Documentation ............................................................................................................................33
11. Revision History........................................................................................................................................................34
2
Data Sheet Revision 2/19/2009
www.intersil.com
ZL2106
1. Electrical Characteristics
Table 1. Absolute Maximum Ratings
Voltage measured with respect to SGND. Operating beyond these limits may cause permanent damage to the device.
Functional operation beyond the Recommended Operating Conditions is not implied.
Parameter
DC Supply Voltage
High Side Supply Voltage
High Side Boost Voltage
Internal MOSFET Reference
Internal Analog Reference
Internal 2.5 V Reference
Logic I/O Voltage
Pin
VDDP, VDDS
BST
BST - SW
VR
VRA
V2P5
EN, CFG, DDC, FC, MGN, PG,
SDA, SCL, SA, SALRT, SS,
SYNC, VTRK, VSET, VSEN
DGND - SGND
PGND - SGND
VR
VRA
V2P5
SW
–
–
All
Comments
Value
-0.3 to 17
-0.3 to 30
-0.3 to 8
-0.3 to 8.5
-0.3 to 6.5
-0.3 to 3
-0.3 to 6.5
Unit
V
V
V
V
V
V
V
Ground Differential
MOSFET Drive Reference
Current
Analog Reference Current
2.5 V Reference Current
Switch node current
Junction Temperature
Storage Temperature
Lead Temperature
±0.3
Internal bias usage
Internal bias usage
Internal bias usage
Peak (sink or source)
20
100
60
10
-55 to 150
-55 to 150
300
V
mA
mA
mA
A
°C
°C
°C
Soldering, 10 s
Table 2. Recommended Operating Conditions and Thermal Information
Symbol
Parameter
VDDS tied to VR, VRA
Input Supply Voltage Range, VDDP, VDDS
(See Figure 13)
Output Voltage Range
1
Operating Junction Temperature Range
Junction to Ambient Thermal Impedance
2
VDDS tied to VR,
VRA floating
VR, VRA floating
V
OUT
T
J
θ
JA
Min
4.5
5.5
7.5
0.54
-40
–
Typ
–
–
–
–
–
35
Max
5.5
7.5
14
5.5
125
–
Unit
V
V
V
V
°C
°C/W
θ
JC
–
5
–
°C/W
Junction to Case Thermal Impedance
3
Notes:
1. Includes margin limits.
2.
θ
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a
low impedance ground plane using multiple vias.
3. For
θ
JC
, the “case” temperature is measured at the center of the exposed metal pad.
3
Data Sheet Revision 2/19/2009
www.intersil.com
ZL2106
Table 3. Electrical Specifications
V
DDP
= V
DDS
= 12 V, T
A
= -40
°C
to 85
°C
unless otherwise noted.
1
Typical values are at T
A
= 25
°C.
Parameter
Input and Supply Characteristics
I
DD
supply current
I
DDS
shutdown current
VR reference output voltage
VRA reference output voltage
V2P5 reference output voltage
Output Characteristics
Output current
Output voltage adjustment range
2
Output voltage setpoint resolution
VSEN output voltage accuracy
VSEN input bias current
Soft start delay duration range
4
Soft start delay duration accuracy
Soft start ramp duration range
Conditions
f
SW
= 200 kHz, no load
f
SW
= 1 MHz, no load
EN = 0 V,
2
No I C/SMBus activity
V
DD
> 8 V, I
VR
< 10 mA
V
DD
> 5.5 V, I
VRA
< 50 mA
I
V2P5
< 50 mA
I
RMS
, Continuous
V
IN
> V
OUT
Set using resistors
Set using I
2
C/SMBus
Includes line, load, temp
VSEN = 5.5 V
Set using SS pin or resistor
Set using I
2
C/SMBus
Turn-on delay (precise mode)
4,5
Turn-on delay (normal mode)
6
Turn-off delay
6
Set using SS pin or resistor
Set using I
2
C/SMBus
Min
–
–
–
6.5
4.5
2.25
–
0.6
–
–
-1
–
2
0.002
–
–
–
2
0
–
-10
-1
–
–
2.0
–
2.25
Typ
11
15
0.6
7.0
5.1
2.5
–
–
10
±0.025
–
110
–
–
±0.25
-0.25/+4
-0.25/+4
–
–
100
–
–
–
1.4
–
–
–
Max
20
30
1
7.5
5.5
2.75
6
5.0
–
–
1
200
20
500
–
–
–
20
200
–
10
1
0.8
–
–
0.4
–
9
1000
5
95
9
–
13
85
65
Unit
mA
mA
mA
V
V
V
A
V
mV
% FS
3
%
µA
ms
s
ms
ms
ms
ms
ms
µs
µA
mA
V
V
V
V
V
A
kHz
%
%
ns
%
mΩ
mΩ
Soft start ramp duration accuracy
Logic Input/Output Characteristics
Logic input bias current
EN,PG,SCL,SDA,SALRT pins
MGN input bias current
Logic input low, V
IL
Multi-mode logic pins
Logic input OPEN (N/C)
Logic input high, V
IH
I
OL
≤
4 mA
Logic output low, V
OL
I
OH
≥
-2 mA
Logic output high, V
OH
Oscillator and Switching Characteristics
Peak (source or sink)
7
Switch node current, I
SW
Switching frequency range
Predefined settings (Table 13)
Switching frequency set-point accuracy
Factory default
8
PWM duty cycle (max)
SYNC pulse width (min)
External clock source
Input clock frequency drift tolerance
R
DS(ON)
of High Side N-channel FETs
I
SW
= 6 A, V
GS
= 6.5 V
I
SW
= 6 A, V
GS
= 12 V
R
DS(ON)
of Low Side N-channel FETs
Notes:
1. Refer to Safe Operating Area in Figure 5 and thermal design guidelines in AN10.
2. Does not include margin limits.
200
-5
–
150
-13
–
–
–
–
–
–
–
60
43
4
Data Sheet Revision 2/19/2009
www.intersil.com
ZL2106
Table 3. Electrical Characteristics (continued)
Parameter
Tracking
VTRK input bias current
VTRK tracking ramp accuracy
VTRK regulation accuracy
Fault Protection Characteristics
UVLO threshold range
UVLO set-point accuracy
UVLO hysteresis
UVLO delay
Power good V
OUT
low threshold
Power good V
OUT
high threshold
Power good V
OUT
hysteresis
Power good delay
VSEN undervoltage threshold
VSEN overvoltage threshold
VSEN undervoltage hysteresis
VSEN undervoltage/ overvoltage fault
response time
Peak current limit threshold
Current limit set-point accuracy
Current limit protection delay
Thermal protection threshold
(junction temperature)
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
V
DDP
= V
DDS
= 12 V, T
A
= -40
°C
to 85
°C
unless otherwise noted.
1
Typical values are at T
A
= 25
°C.
Conditions
VTRK = 5.5 V
100% Tracking, V
OUT
- VTRK
100% Tracking, V
OUT
- VTRK
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Factory default
Factory default
Using pin-strap or resistor
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Min
–
-100
-1
2.85
-150
–
0
–
–
–
–
2
0
–
0
–
0
–
–
5
–
0.2
–
–
1
–
-40
–
Typ
110
–
–
–
–
3
–
–
90
115
5
–
–
85
–
115
–
5
16
–
–
–
±10
5
–
125
–
15
Max
200
100
1
16
150
–
100
2.5
–
–
–
20
500
–
110
–
115
–
–
60
9.0
9.0
–
–
32
–
125
–
Unit
µA
mV
%
V
mV
%
%
µs
% V
OUT
% V
OUT
%
ms
s
% V
OUT
% V
OUT
% V
OUT
% V
OUT
% V
OUT
µs
µs
A
A
% FS
3
t
SW 10
t
SW 10
°C
°C
°C
Thermal protection hysteresis
Notes:
3. Percentage of Full Scale (FS) with temperature compensation applied.
4. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this
delay period to approx 2 ms, where in normal mode it may vary up to 4 ms.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable. Precise ramp
timing mode is automatically disabled for a self-enabled device (EN pin tied high).
6. The devices may require up to a 4 ms delay following the assertion of the enable signal (normal mode) or following the de-
assertion of the enable signal. Precise mode requires Re-Enable delay = T
OFF
+T
FALL
+10 µs.
7. Switch node current should not exceed I
RMS
of 6 A.
8. Factory default is the initial value in firmware. The value can be changed via PMBus commands.
9. Maximum duty cycle is limited by the equation MAX_DUTY(%) = [1 - (150×10
-9
× f
SW
)] × 100 and not to exceed 95%.
10. t
SW
= 1/f
SW
, where f
SW
is the switching frequency.
5
Data Sheet Revision 2/19/2009
www.intersil.com
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