ZL2005P
Data Sheet
February 18, 2009
FN6849.0
Digital-DC™ Controller with Drivers and POLA/DOSA Trim
Description
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a com-
pact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple low-voltage power
domains on a single PCB.
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
Features Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.54 V to 5.5 V output range (with margin)
• Optional output voltage setting with VADJ pin
• ± 1% output accuracy
• Internal 3 A drivers support >40 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I
2
C/SMBus communication
• Output overvoltage and overcurrent protection
• Internal non-voltatile memory (NVM)
• PMBus compliant
Applications
•
•
•
Servers/storage equipment
Telecom/datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
SS (0,1)
VTRK
MGN
SYNC
VADJ
POWER
MANAGEMENT
LDO
BST
GH
SW
GL
ISENA
ISENB
DRIVER
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
CURRENT
SENSE
TEMP
SENSOR
SCL
SDA
SALRT
I
2
C
MONITOR
ADC
SA (0,1)
XTEMP VSEN
PGND SGND DGND
Figure 1. Block Diagram
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ZL2005P
Table of Contents
1
2
3
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZL2005P Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
ZL2005 - ZL2005P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Internal Bias Regulators and Input Supply Connections. . . . . . . . . . . . . . . . . . . . . .
5.2
High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Soft Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Selecting Power Train Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Current Limit Threshold Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Non-Linear Response Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Efficiency Optimized Driver Dead-time Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Input Undervoltage Lockout (UVLO) Standard Mode . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
I2C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
I2C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Non-volatile Memory and Device Security Features. . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
7
9
10
10
10
11
12
12
14
14
14
14
18
19
20
20
22
25
28
29
29
30
30
30
31
31
32
32
33
33
34
34
35
36
37
37
38
39
39
39
5
6
7
8
2
FN6849.0
February 18, 2009
ZL2005P
1
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the recommended
operating conditions is not implied. Unless otherwise specified, all voltages are measured with respect to SGND.
Parameter
Pin(s)
Value
Unit
DC supply voltage
Logic I/O voltage
Analog input voltages
VDD
DLY(0,1), EN, ILIM(0,1),
MGN, PG, SA(0,1), SALRT,
SCL, SDA, SS(0,1), SYNC,
VADJ, UVLO, V(0,1)
ISENB, VSEN, VTRK,
XTEMP,
ISENA
VR
V25
BST
GH
GL
BST, SW
SW
SW
DGND, SGND, PGND
–
–
–
-0.3 to 17
-0.3 to 6.5
V
V
-0.3 to 6.5
-1.5 to +30
-0.3 to 6.5
120
-0.3 to 3
120
-0.3 to +30
(V
SW
- 0.3) to (V
BST
+0.3)
(PGND-0.3) to (VR+0.3+PGND)
-0.3 to 8
(PGND-0.3) to 30
(PGND-5) to 30
-0.3 to +0.3
-55 to 150
-55 to 150
300
V
V
V
mA
V
mA
V
V
V
V
V
V
V
o
C
o
o
MOSFET drive reference
Logic reference
High-side supply voltage
High-side drive voltage
Low-side drive voltage
Boost to switch differential voltage
(V
BST
- V
SW
)
Switch node continuous
Switch node transient
(<100 ns)
Ground voltage differential
(V
DGND
-V
SGND
), (V
PGND
-V
SGND
)
Junction temperature
Storage temperature range
Lead temperature
(soldering, 10 s)
C
C
3
FN6849.0
February 18, 2009
ZL2005P
Table 2. Recommended Operating Conditions and Thermal Information
Parameter
Symbol
Min
Typ
Max
Unit
V
R
tied to V
DD
(Figure 9)
V
R
floating (Figure 9)
Output Voltage Range
V
OUT
(RDSON sensing)
Output Voltage Range
V
OUT
(DCR sensing)
Operating Junction Temperature Range
T
J
Junction to Ambient Thermal
Θ
JA
Impedance
1
Θ
JC
Junction to Case Thermal Impedance
2
Input Supply Voltage Range, V
DD
NOTES:
3.0
4.5
0.54
0.6
-40
–
–
–
–
–
35
5
5.5
14
5.5
3.6
3
125
–
–
V
V
V
V
°C
°C/W
°C/W
1.
Θ
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane
using multiple vias.
2. For
Θ
JC
, the “case” temperature is measured at the center of the exposed metal pad
3. With margin
Table 3. Electrical Specifications
Unless otherwise specified V
DD
= 12 V, T
A
= -40
o
C to +85
o
C. Typical values are at T
A
= 25
o
C.
Parameter
Condition
Min
Input and Supply Characteristics
Typ
Max
Unit
Supply current (I
DD
)
(No load on GH and GL)
Standby supply current (I
DD
)
VR reference voltage (V
R
)
V25 reference voltage (V
25
)
Output Characteristics
f
SW
= 200 kHz
f
SW
= 1,000 kHz
EN = Low
no I
2
C/SMBus activity
V
DD
≥
6 V
I
VR
< 50 mA
V
R
≥
3 V
I
V25
< 50 mA
–
–
–
4.5
2.25
0.6
–
–
-1
–
-100
-50
-100
-1
-100
0.007
–
16
25
2
5.2
2.5
–
10
Table 8
±0.025
30
50
5
5.5
2.75
5.5
–
–
1
200
100
50
100
1
100
500
–
mA
mA
mA
V
V
V
mV
% of
F.S.
1
%
µA
mV
mV
µA
µA
µA
s
ms
FN6849.0
February 18, 2009
Output voltage adjustment range
Set using resistors on V(0,1)
Set using resistor on VADJ
Set using I
2
C/SMBus
Output voltage accuracy
VSEN input bias current
Current sense differential input
voltage (ground referenced)
Current sense differential input
voltage (V
OUT
referenced)
Current sense input bias current
Current sense input bias current
(V
OUT
referenced,
V
OUT
<= 3.6V)
Soft start delay duration range
Soft start delay duration accuracy
4
Output voltage setpoint resolution
Over line and load
VSEN = 5.5 V
V
ISENA
- V
ISENB
V
ISENA
- V
ISENB
Ground referenced
ISENA
ISENB
Configurable via I
2
C/SMBus
110
–
–
–
–
–
–
6
ZL2005P
Table 3. Electrical Specifications
Unless otherwise specified V
DD
= 12 V, T
A
= -40
o
C to +85
o
C. Typical values are at T
A
= 25
o
C. (Continued)
Parameter
Condition
Min
Typ
Max
Unit
Soft start ramp duration range
Soft start ramp duration accuracy
Logic Input/Output Characteristics
Configurable via I
2
C/SMBus
0
–
-10
–
–
2
–
2.25
200
–
100
–
–
1.4
–
–
–
–
–
–
–
–
4.5
3
0.8
0.5
2.5
1.8
1.2
0.5
200
–
10
0.8
–
–
0.4
–
1400
5
–
–
13
–
–
2
2
–
–
2
2
ms
µs
μA
V
V
V
V
V
kHz
%
%
ns
%
V
A
Ω
Ω
A
A
Ω
Ω
Logic input bias current
Logic input low threshold (V
IL
)
Logic input OPEN (N/C)
Logic input high threshold (V
IH
)
Logic output low (V
OL
)
Logic output high (V
OH
)
EN, PG, SCL, SDA, SALRT
Multi-mode logic pins
I
OL
<=
4 mA
I
OH
>=
- 2 mA
Oscillator and Switching Characteristics
Switching frequency range
Switching frequency setpoint
accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width
Input clock frequency drift tolerance
Gate Drivers
Predefined settings
(See table 13)
Factory default
External clock signal
-5
95
150
-13
–
High-side driver voltage
(V
BST
- V
SW
)
High-side driver peak gate drive
current (pull down)
High-side driver pull-up resistance
High-side driver pull-down
resistance
Low-side driver peak gate drive
current (pull-up)
Low-side driver peak gate drive
current (pull-down)
Low-side driver pull-up resistance
Low-side driver pull-down
resistance
Switching timing
GH rise and fall time
GL rise and fall time
Tracking
(V
BST
- V
SW
) = 4.5 V
(V
BST
- V
SW
) = 4.5 V,
(V
BST
- V
GH
) = 50 mV
(V
BST
- V
SW
) = 4.5 V,
(V
GH
- V
SW
) = 50 mV
V
R
= 5 V
V
R
= 5 V
V
R
= 5 V,
(V
R
- V
GL
) = 50 mV
V
R
= 5 V,
(V
GL
- PGND) = 50 mV
(V
BST
- V
SW
) = 4.5 V,
C
LOAD
= 2.2 nF
V
R
= 5 V,
C
LOAD
= 2.2 nF
VTRK = 5.5 V
VTRK >= 0.3 V
2
–
–
–
–
–
–
–
–
–
– 100
5
5
110
20
20
200
100
ns
ns
µA
mV
VTRK input bias current
VTRK tracking threshold
5
FN6849.0
February 18, 2009
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