NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ZL2006
DATASHEET
FN6848
Rev 2.00
February 23, 2011
ZL2005
Digital-DC™ Integrated Power Management and Conversion IC
Description
The ZL2005 is an innovative mixed-signal power
management and conversion IC that combines a com-
pact, efficient, synchronous DC/DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs’ Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple, low-voltage power
domains on a single PCB.
The ZL2005 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 3.3 V input to a multi-phase supply operating
from a 12 V input. The ZL2005 eliminates the need
for complicated power supply managers as well as
numerous external discrete components.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005 uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
Features
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Power good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I
2
C/SMBus communication
• Output overvoltage and overcurrent protection
• PMBus compliant
Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.6 V to 5.5 V output range
• ± 1% output accuracy
• Internal 3 A drivers support >30 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Applications
•
•
•
•
Servers/storage equipment
Telecom/datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
Point of load converters
V (0,1)
SS (0,1)
VTRK
MGN
SYNC
POWER
MANAGEMENT
LDO
BST
GH
SW
GL
ISENA
ISENB
DRIVER
NON-
VOLATILE
MEMORY
SCL
SDA
SALRT
PWM
CONTROLLER
CURRENT
SENSE
TEMP
SENSOR
I
2
C
MONITOR
ADC
SA (0,1)
VSEN
VTRK
TACH XTEMP
PGND SGND DGND
Figure 1. Block Diagram
Figure 2. Efficiency vs. Load Current
FN6848 Rev 2.00
February 23, 2011
Page 1 of 39
ZL2005
Table of Contents
1
2
3
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZL2005 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Internal Bias Regulators and Input Supply Connections. . . . . . . . . . . . . . . . . . . . . .
5.2
High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Soft Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Selecting Power Train Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Current Limit Threshold Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Non-Linear Response Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Efficiency Optimized Driver Dead-time Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Input Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
I2C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
I2C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Fan Monitoring using the TACH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
8
10
11
11
12
13
13
15
15
15
15
16
17
18
18
20
23
26
27
28
29
29
29
30
30
31
31
33
33
33
34
34
35
35
36
36
37
38
5
6
7
8
FN6848 Rev 2.00
February 23, 2011
Page 2 of 39
ZL2005
1
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the recommended
operating conditions is not implied. Unless otherwise specified, all voltages are measured with respect to SGND.
Parameter
Pin(s)
Value
Unit
DC supply voltage
Logic I/O voltage
Analog input voltages
MOSFET drive reference
Logic reference
High-side supply voltage
High-side drive voltage
Low-side drive voltage
Boost to switch differential voltage
(V
BST
- V
SW
)
Switch node continuous
Switch node transient
(<100 ns)
Ground voltage differential
(V
DGND
-V
SGND
), (V
PGND
-V
SGND
)
Junction temperature
Storage temperature range
Lead temperature
(soldering, 10 s)
ESD HBM tolerance
(100 pF, 1.5 k)
VDD
DLY(0,1), EN, ILIM(0,1),
MGN, PG, SA(0,1), SALRT,
SCL, SDA, SS(0,1), SYNC,
TACH, UVLO, V(0,1)
ISENB, VSEN, VTRK,
XTEMP,
ISENA
VR
V25
BST
GH
GL
BST, SW
SW
SW
DGND, SGND, PGND
–
–
–
All
-0.3 to 17
-0.3 to 6.5
V
V
-0.3 to 6.5
-1.5 to +30
-0.3 to 6.5
120
-0.3 to 3
120
-0.3 to +30
(V
SW
- 0.3) to (V
BST
+0.3)
(PGND-0.3) to (VR+0.3+PGND)
-0.3 to 8
(PGND-0.3) to 30
(PGND-5) to 30
-0.3 to +0.3
-55 to 150
-55 to 150
300
2
V
V
V
mA
V
mA
V
V
V
V
V
V
V
o
C
o
o
C
C
kV
FN6848 Rev 2.00
February 23, 2011
Page 3 of 39
ZL2005
Table 2. Recommended Operating Conditions and Thermal Information
Parameter
Symbol
Min
Typ
Max
Unit
Input Supply Voltage Range, V
DD
Output Voltage Range
Operating Junction Temperature Range
Junction to Ambient Thermal
Impedance
1
Junction to Case Thermal Impedance
2
NOTES:
V
R
tied to V
DD
(Figure 9)
V
R
floating (Figure 9)
V
OUT
T
J
3.0
4.5
0.6
-40
–
–
–
–
–
35
5
5.5
14
5.5
125
–
–
V
V
V
°C
°C/W
°C/W
JA
JC
1.
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane
using multiple vias.
2. For
JC
, the “case” temperature is measured at the center of the exposed metal pad
Table 3. Electrical Specifications
Parameter
Input and Supply Characteristics
Unless otherwise specified V
DD
= 12 V, T
A
= -40
o
C to +85
o
C. Typical values are at T
A
= 25
o
C.
Condition
Min
5
Typ
Max
5
Unit
Supply current (I
DD
)
(No load on GH and GL)
Standby supply current (I
DD
)
VR reference voltage (V
R
)
V25 reference voltage (V
25
)
Output Characteristics
f
SW
= 200 kHz
f
SW
= 2,000 kHz
EN = Low
no I
2
C/SMBus activity
V
DD
6 V
I
VR
< 50 mA
V
R
3 V
I
V25
< 50 mA
–
–
–
4.5
2.25
0.6
16
25
2
5.2
2.5
–
10
±0.025
–
110
–
–
–
30
50
5
5.5
2.75
5.5
–
–
1
200
100
100
100
mA
mA
mA
V
V
V
mV
% of
F.S.
1
%
µA
mV
mV
µA
Output voltage adjustment range
Set using resistors
Output voltage setpoint resolution
Output voltage accuracy
VSEN input bias current
Current sense differential input
voltage (ground referenced)
Current sense differential input
voltage ( V
OUT
referenced)
Current sense input bias current
NOTE:
1. Percentage of Full Scale (F.S.) with temperature compensation applied
–
–
-1
–
-100
-100
-100
Set using I
2
C/SMBus
Over line, load and temperature
VSEN = 5.5 V
V
ISENA
- V
ISENB
V
ISENA
- V
ISENB
Ground referenced
Current sense input bias current
(V
OUT
referenced,
V
OUT
<= 3.6V)
ISENA
ISENB
-1
-100
–
–
1
100
µA
µA
FN6848 Rev 2.00
February 23, 2011
Page 4 of 39
ZL2005
Unless otherwise specified V
DD
= 12 V, T
A
= -40
o
C to +85
o
C. Typical values are at T
A
= 25
o
C. (Continued)
Parameter
Condition
Min
5
Typ
Max
5
Unit
Table 3. Electrical Specifications
Soft start delay duration range
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
Logic Input/Output Characteristics
Set using DLY pin or resistor
Configurable via I
2
C/SMBus
Set using SS pin or resistor
Configurable via I
2
C/SMBus
7
0.007
–
0
0
–
–
–
6
–
–
100
200
500
–
200
200
–
ms
s
ms
ms
ms
µs
Logic input bias current
MGN input bias current
Logic input low threshold (V
IL
)
Logic input OPEN (N/C)
Logic input high threshold (V
IH
)
Logic output low (V
OL
)
Logic output high (V
OH
)
EN, PG, SCL, SDA, SALRT,
TACH
During configuration restore
-10
-1
-1
–
–
–
–
–
1.4
–
–
–
–
–
–
–
–
–
–
–
10
1
1
0.8
–
–
0.4
–
2000
5
–
–
13
–
500
10
A
mA
mA
V
V
V
V
V
kHz
%
%
ns
%
ns
Hz
%
Multi-mode logic pins
I
OL
<=
4 mA
I
OH
=
- 2 mA
–
2
–
2.25
200
Oscillator and Switching Characteristics
Switching frequency range
Switching frequency setpoint
accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width
Input clock frequency drift tolerance
Tachometer Characteristics
Predefined settings
(See table 14)
Factory default
External clock signal
-5
95
150
-13
150
1
-10
TACH pulse width
TACH frequency range
TACH accuracy
FN6848 Rev 2.00
February 23, 2011
Page 5 of 39
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