FEDL610Q482-02
Issue Date: May.9, 2014
ML610Q482/ML610482
8-bit Microcontroller
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I
2
C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are
incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
The ML610Q482P/ ML610482P supporting industrial temperature -40°C to +85°C, are also available.
FEATURES
•
CPU
−
8-bit RISC CPU (CPU name: nX-U8/100)
−
Instruction system: 16-bit instructions
−
Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
−
On-Chip debug function (ML610Q482)
−
Minimum instruction execution time
30.5
µs
(@32.768 kHz system clock)
0.244µs (@4.096 MHz system clock)
•
Internal memory
−
ML610Q482
Internal 64KByte Flash ROM (32K×16 bits) (including unusable 1KByte TEST area)
Internal 4KByte Data RAM (4096×8 bits)
−
ML610482
Internal 64KByte Mask ROM (32K×16 bits) (including unusable 1KByte TEST area)
Internal 4KByte Data RAM (4096×8 bits)
•
Interrupt controller
−
2 non-maskable interrupt sources (Internal source: 1, External source: 1)
−
18 maskable interrupt sources (Internal sources: 14, External sources: 4)
•
Time base counter
−
Low-speed time base counter
×1
channel
Frequency compensation (Compensation range: Approx.
−488ppm
to +488ppm. Compensation accuracy: Approx.
0.48ppm)
−
High-speed time base counter
×1
channel
•
Watchdog timer
−
Non-maskable interrupt and reset
−
Free running
−
Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s @32.768 kHz)
•
Timers
−
8 bits
×
4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
−
Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
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FEDL610Q482-02
ML610Q482/ML610482
•
PWM
−
Resolution 16 bits
×
1 channel
•
Synchronous serial port
−
Master/slave selectable
−
LSB first/MSB first selectable
−
8-bit length/16-bit length selectable
•
UART
−
TXD/RXD
×
1 channel
−
Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
−
Positive logic/negative logic selectable
−
Built-in baud rate generator
•
I
2
C bus interface
−
Master function only
−
Fast mode (400 kbps@4MH½), standard mode (100 kbps@1MH½, 50kbps@500kHz)
•
Buzzer driver
−
4 output modes, 8 frequencies, 16 duty levels
•
RC oscillation type A/D converter
−
24-bit counter
−
Time division
×
2 channels
•
Analog Comparator
−
Operating voltage:
V
DD
=1.8V½3.6V
−
Common mode input voltage:
0.2V½VDD－1.0V
−
Input offset voltage:
50mV(max)
−
Interrupt allow edge selection and sampling selection
•
General-purpose ports
−
Non-maskable interrupt input port
×
1 channel
−
Input-only port
×
6 channels (including secondary functions)
−
Output-only port
×
4 channels (including secondary functions)
−
Input/output port
×
22 channels (including secondary functions)
•
Reset
−
Reset through the RESET_N pin
−
Power-on reset generation when powered on
−
Reset when oscillation stop of the low-speed clock is detected
−
Reset by the watchdog timer (WDT) overflow
•
Power supply voltage detect function
−
Judgment voltages:
One of 16 levels
−
Judgment accuracy:
±2%
(Typ.)
•
Clock
−
Low-speed clock: (This LSI can not guarantee the operation withou½ low-speed clock)
Crystal oscillation (32.768 kHz/38.4KHz)
−
High-speed clock:
Built-in RC oscillation (500 kHz)
Built-in PLL oscillation (8.192 MHz
±2.5%),
crystal/ceramic oscillation (4.096 MHz), external clock
−
Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
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FEDL610Q482-02
ML610Q482/ML610482
•
Power management
−
HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
−
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
−
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
−
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
•
Guaranteed operating range
−
Operating temperature:
−20°C
to +70°C (P version:
−40°C
to +85°C)
−
Operating voltage: V
DD
= 1.1V to 3.6V
•
Product name – S
upported
Function
Operating
temperature
-20°C to +70°C
- Chip (Die) -
ROM type
Product availability
ML610Q482-½½½WA
Flash ROM
Yes
ML610Q482P-½½½WA
Flash ROM
-40°C to +85°C
Yes
ML610482-½½½WA
Mask ROM
-20°C to +70°C
Yes
ML610482P-½½½WA
Mask ROM
-40°C to +85°C
Yes
-48-pin plastic
TQFP -
ML610Q482-½½½TB
ROM type
Operating
temperature
-20°C to +70°C
Product availability
Flash ROM
Yes
ML610Q482P-½½½TB
Flash ROM
-40°C to +85°C
Yes
ML610482-½½½TB
Mask ROM
-20°C to +70°C
-
ML610482P-½½½TB
Mask ROM
-40°C to +85°C
-
xxx: ROM code number
Q:Flash ROM version
P: Wide range temperature version
WA: Chip
TB: TQFP
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FEDL610Q482-02
ML610Q482/ML610482
BLOCK DIAGRAM
ML610Q482 Block Diagram
Figure 1 show the block diagram of the ML610Q482.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
4096byte
Interrupt
Controller
INT
1
INT
4
Power
INT
1
INT
4
INT
1
UART
INT
1
I
2
C
TBC
INT
1
PWM
8bit Timer
×4
Buzzer
INT
9
BZ0*
PWM0*
SDA*
SCL*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Flash)
64Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DDX
OSC
RESET &
TEST
INT
1
SSIO
SCK0*
SIN0*
SOUT0*
WDT
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
RC-ADC
×2
BLD
NMI
P00 to P03
P10, P11
GPIO
P20, P21, P22, P24
P30 to P35
P40 to P47
PA0 to PA7
CMPP
CMPM
Analog
Comparator
INT
1
Figure 1 ML610Q482 Block Diagram
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FEDL610Q482-02
ML610Q482/ML610482
ML610482 Block Diagram
Figure 2 show the block diagram of the ML610482.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
4096byte
Interrupt
Controller
INT
1
INT
4
Power
INT
1
INT
4
INT
1
UART
INT
1
I
2
C
TBC
INT
1
PWM
8bit Timer
×4
Buzzer
INT
5
BZ0*
PWM0*
SDA*
SCL*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Mask ROM)
64Kbyte
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DDX
OSC
RESET &
TEST
INT
1
SSIO
SCK0*
SIN0*
WDT
IN0*
CS0*
RS0*
RT0*
RCT0*
RCM*
IN1*
CS1*
RS1*
RT1*
RC-ADC
×2
BLD
NMI
P00 to P03
P10, P11
GPIO
P20, P21, P22, P24
P30 to P35
P40 to P47
PA0 to PA7
CMPP
CMPM
Analog
Comparator
INT
1
*
Secondary
function or Tertiary function
Figure 2 ML610482 Block Diagram
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