SED1181
SED1181
CMOS LCD 64-SEGMENT DRIVER
s
DESCRIPTION
The SED1181 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through
LCD controller, and serially transferred through 16
×
4 shift register. The display data is held in a 64-bit latch
circuit. The LSI converts the level of the latched data to an LCD drive waveform.
The SED1181 is used in conjunction with the SED1191 (64-bit row driver) to drive a large-capacity dot-matrix
LCD panel.
s
FEATURES
•
Low-power CMOS technology
•
64-bit segment (column) driver
•
Serial 2-bit input data
•
Duty cycle ..................................... 1/64 to 1/128
•
Daisy chain enable support
s
SYSTEM BLOCK DIAGRAM
•
Wide range of LCD voltage .......... –14V to –25V
•
Supply voltage ................................. 5.0V
±
10%
QFP1-80 pin (F
•
Package ................................ QFP5-80 pin (F ))
0A
5A
D0 ~ D1 (SERIAL DATA)
XSCL
LP, FR
YSCL
YD
LCD
CONTR
SED1181
64
SED1181
64
SED1181
64
SED1181
64
SED1191
64
256 SEG
×
64 COM
DUTY: 1/64
435
SED1181
s
BLOCK DIAGRAM
0
1
SEG
31
LCD Driver
Level Shift
Latch
D0
LP
XSCL
D1
Voltage Control
Shift Register
32 bit
32 bit
32 bit
32 bit
DO0
Shift Register
Latch
32 bit
32 bit
32 bit
32 bit
DO1
FR
5
V
SS
V
DD
V2
V3
V
SSH
Level Shifter
LCD Driver
32
33
SEG
63
s
PIN CONFIGURATION
64
41
65
40
SED1181
80
25
1
24
436
SED1181
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG 9
SEG 8
Number
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
SEG 7
SEG 6
SEG 5
SEG 4
SEG 3
SEG 2
SEG 1
SEG 0
DO0
NC
NC
D1
D0
XSCL
LP
FR
SEG32
SEG33
SEG34
SEG35
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
V
SSH
V2
V3
V
SS
V
DD
DO1
NC
NC
SEG31
SEG30
SEG29
SEG28
s
PIN DESCRIPTION
Pin Name
D0
D1
SEG0 to SEG 31
SEG 32 to SEG 63
XSCL
LP
FR
DO0
DO1
V
DD
, V
SS
V
SSH
, V
2
, V
3
Function
Serial data input to upper shift register
Serial data input to lower shift register
Segment driver outputs supplied by the upper shift register
Segment driver outputs supplied by the lower shift register
Data shift clock input
Data latch pulse input
LCD frame signal input
Serial data output from upper shift register
Serial data output from lower shift register
Logic circuitry power inputs
LCD drive power inputs
V
DD
> V2 > V3 > V
SSH
437
SED1181
s
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage (1)
Supply voltage (2)
Input voltage
Operating temperature
Storage temperature
Soldering temperature, time
Notes:
1. All voltages are based on a V
DD
of 0V.
2. V2 and V3 must satisfy the condition V
DD
≥
V2, V3
≥
V
SSH
.
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced during the soldering process, so care should be taken to avoid thermally
stressing the package during board assembly.
Symbol
V
SS
V
SSH
V2, V3
V
I
T
opr
T
stg
T
sol
Ratings
–7.0 to +0.3
–28.0 to +0.3
V
SS
-0.3 to +0.3
–20 to +75
–65 to +150
260°C, 10 sec (at lead)
Unit
V
V
V
°C
°C
°C
/ Sec
438
SED1181
•
DC Electrical Characteristics
(V
DD
= 0V, V
SS
= –5.0V
±
10%, T
a
= –20 to 75°C)
Condition
Rating
Min
–5.5
V
SSH
V
SSH
–25.0
0.2V
SS
V
SS
–0.3
I
OH
= –0.6 mA
I
OL
= 0.6 mA
0 V
≤
V
I
≤
V
SS
0 V
≤
V
O
≤
V
SS
–0.4
—
—
—
—
—
T
a
= 25°C
V
SSH
= –14.0 V
V
OH
= V
DD
–0.5 V
V
OL
= V
SSH
+0.5 V
SEG./ bit
—
—
Typ
–5.0
—
—
—
—
—
—
—
0.05
0.05
—
1/60
5.0
3.0
Max
–4.5
V
DD
V
DD
–14.0
V
DD
+0.3
0.8V
SS
—
V
SS
+0.4
2.0
5.0
6.0
—
8.0
6.0
Unit
V
V
V
V
V
V
V
V
µA
µA
MHz
sec
pF
kΩ
Parameter
Supply voltage (1)
Symbol
V
SS
V
2
V
3
V
SSH
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
XSCL
FR
C
I
R
SEG
Supply voltage (2)
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Shift clock
Frame signal
Input capacitance
Segment output on
resistance
Quiescent current
I
Q
V
SSH
= –25.0V, V
SS
= –5.5 V, V
I
= V
DD
V
SS
= –5.0 V,
V
IH
= V
DD
,
V
IL
= V
SS
,
FR period = 130
µs
(duty 50%),
LP period = 130
µS,
XSCL frequency = 1.5 MHz
(duty 50%)
V
SS
= –4.5 V,
V
2
= –4.0 V,
V
3
= –16.0 V,
V
SSH
= –20.0 V,
Other parameters as for I
SSOP
—
0.05
30
µA
Logic circuit
I
SSOP
—
850
1200
µA
LCD circuit operating
current
I
SSHOP
—
70
100
µA
Notes:
1. All voltages are based on a V
DD
of 0V.
2. The driver will operate with a value of V
SSH
in this range, however the “on” source impedance of a segment drive can be higher
than at the recommended value of V
SSH
. It is recommended that the drivers are tested with the LCD panel they will be used
with to determine a suitable value for V
SSH
.
439
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