93LC76/86
8K/16K 2.5V Microwire
®
Serial EEPROM
FEATURES
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5
µ
A standby current (typical) at 3.0V
• ORG pin selectable memory configuration
1024 x 8 or 512 x 16 bit organization (93LC76)
2048 x 8 or 1024 x 16 bit organization (93LC86)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC package
• Temperature ranges available
- Commercial (C)
0
°
C to +70
°
C
- Industrial (I)
-40
°
C to +85
°
C
PACKAGE TYPES
DIP Package
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
ORG
V
SS
93LC76/86
SOIC Package
1
2
3
4
8
7
6
5
93LC76/86
CS
CLK
DI
DO
V
CC
PE
ORG
V
SS
BLOCK DIAGRAM
V
CC
V
SS
DESCRIPTION
The Microchip Technology Inc. 93LC76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93LC76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.
Memory
Array
Address
Decoder
Address
Counter
Data
Register
DI
Output
Buffer
DO
PE
CS
Mode
Decode
Logic
CLK
Clock
Generator
Microwire is a registered trademark of National Semiconductor Incorporated.
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21131C-page 1
93LC76/86
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
1.2
AC Test Conditions
AC Waveform:
V
LO
= 2.0V
V
HI
= Vcc - 0.2V
V
HI
= 4.0V for
(Note 1)
(Note 2)
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
Timing Measurement Reference Level
Input
Output
Note 1: For V
CC
≤
4.0V
2: For V
CC
> 4.0V
0.5 V
CC
0.5 V
CC
TABLE 1-1:
Name
CS
CLK
DI
DO
V
SS
ORG
PE
V
CC
PIN FUNCTION TABLE
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
V
CC
= +2.5V to +6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Symbol
V
IH1
V
IH2
V
IL1
V
IL2
V
OL1
V
OL2
V
OH1
V
OH2
I
LI
I
LO
C
INT
I
CC
write
I
CC
read
Min.
2.0
0.7 V
CC
-0.3
-0.3
—
—
2.4
V
CC
-0.2
-10
-10
—
—
—
Max.
V
CC
+1
V
CC
+1
0.8
0.2 V
CC
0.4
0.2
—
—
10
10
7
Units
V
V
V
V
V
V
V
V
µ
A
µ
A
pF
Conditions
V
CC
≥
2.7V
V
CC
< 2.7V
V
CC
≥
2.7V
V
CC
< 2.7V
I
OL
= 2.1 mA; V
CC
= 4.5V
I
OL
=100
µ
A; V
CC
= V
CC
Min.
I
OH
= -400
µ
A; V
CC
= 4.5V
I
OH
= -100
µ
A; V
CC
= V
CC
Min.
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to V
CC
(Note Note:)
Tamb = +25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V
F
CLK
= 3 MHz; V
CC
= 5.5V
F
CLK
= 1 MHz; V
CC
= 3.0V
CLK = CS = 0V; V
CC
= 5.5V
CLK = CS = 0V; V
CC
= 3.0V
3
mA
1
mA
500
µ
A
µ
A
—
100
Standby current
I
CCS
µ
A
30
Note:
This parameter is periodically sampled and not 100% tested.
DS21131C-page 2
Preliminary
©
1996 Microchip Technology Inc.
93LC76/86
2.0
PRINCIPLES OF OPERATION
2.3
When the ORG pin is connected to V
CC
, the x16 orga-
nization is selected. When it is connected to ground, the
x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/BUSY status dur-
ing a programming operation. The READY/BUSY sta-
tus can be verified during an Erase/Write operation by
polling the DO pin; DO low indicates that programming
is still in progress, while DO high indicates the device is
ready. The DO will enter the high impedance state on
the falling edge of the CS.
Erase/Write Enable and Disable
(EWEN, EWDS)
The 93LC76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V
CC
is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should fol-
low all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.
2.1
START Condition
2.4
Data Protection
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
During power-up, all programming modes of operation
are inhibited until V
CC
has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
CC
has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.
©
1996 Microchip Technology Inc.
Preliminary
DS21131C-page 5
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