550AB107M878BGR datasheet, PDF

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550AB107M878BGR: DescriptionLVPECL Output Clock Oscillator, 107.878MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size556KB，44 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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550AB107M878BGR Overview

LVPECL Output Clock Oscillator, 107.878MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

550AB107M878BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	30 ppm
frequency stability	100%
JESD-609 code	e4
Manufacturer's serial number	550
Installation features	SURFACE MOUNT
Nominal operating frequency	107.878 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	177.8mm x 127.0mm x 41.91mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

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Si550

O L TA G E

- C

O N T R O L L E D

R Y S TA L

S C I L L A T O R

(V CX O)

10 MH

Z T O

1.4 G H

Features

Available with any-rate output

frequencies from 10 MHz to

945 MHz and selected frequencies

to 1.4 GHz

3rd generation DSPLL

with

superior jitter performance

3x better frequency stability than

SAW based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, & CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Lead-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Pin Assignments:

See page 6.

(Top View)

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXO’s where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

GND

CLK–

CLK+

Functional Block Diagram

CLK–

CLK+

Fixed

Frequency

Any-rate

10-1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 0.5 7/06

Si550

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