97SD3248
1.5Gb SDRAM
8-Meg X 48-Bit X 4-Banks
Logic Diagram
(One Amplifier)
Memory
F
EATURES
:
• 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
SEL
TH
> 85 MeV/mg/cm2 @ 25°C
• JEDEC Standard 3.3V Power Supply
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125 °C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 132 Lead Quad Stack Pack Flat Package
D
ESCRIPTION
:
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 1.5 Gigabits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
DRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time
Maxwell Technologies’ patented R
AD
-P
AK
®
packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, R
AD
-P
AK
®
provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
All data sheets are subject to change without notice
02.04.05 Rev 3
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2005 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Pinout Description
97SD3248
Vcc
NC
Vss
NC
D47
D31
D15
VSSQ
VCCQ
NC
CS6
CS4
CS2
CLK2
NC
DQM6
DQM4
DQM2
D46
D30
D14
VCCQ
VSSQ
D45
D29
D13
D44
D28
D12
NC
Vss
NC
Vcc
Vcc
Vss
NC
CKE6
CKE5
CKE4
CKE3
CKE2
CKE1
WE
A12
VSSQ
VCCQ
A11
A10
A9
A8
A7
A6
A5
VCCQ
VSSQ
A4
A3
A2
A1
A0
BA1
BA0
RAS
CAS
Vss
Vcc
Vcc
NC
Vss
NC
NC
VSSQ
VCCQ
NC
CS5
CS3
CS1
CLK1
NC
DQM5
DQM3
DQM1
D35
D19
D3
VCCQ
VSSQ
D34
D18
D2
D33
D17
D1
D32
D16
D0
Vss
NC
Vcc
Memory
Vcc
Vss
NC
D43
D27
D11
D42
D26
D10
D41
D25
D9
VSSQ
VCCQ
D40
D24
D8
D39
D23
D7
VCCQ
VSSQ
D38
D22
D6
D37
D21
D5
D36
D20
D4
Vss
Vcc
The 97SD3248 Consists of 6, 8-Meg X 8-Bit X 4-Banks, die.
CKE 1-6, CS 1-6 and DQM 1-6 correspond to one of the die:
CKE1, CS1 and DQM1 control D0 - D7
CKE2, CS2 and DQM2 control D8 - D15
CKE3, CS3 and DQM3 control D16 - D23
CKE4, CS4 and DQM4 control D24 - D31
CKE5, CS5 and DQM5 control D32 - D39
CKE6, CS6 and DQM6 control D40 - D47
02.04.05 Rev 3
All data sheets are subject to change without notice
2
©2005 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
‘
97SD3248
T
ABLE
1. A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on any pin relative to V
SS
Supply voltage relative to V
SS
Short circuit output current
Operating Temperature
Storage Temperature
S
YMBOL
V
IN
V
OUT
V
CC
I
OUT
T
OPR
T
STG
M
AX
-0.5 to VCC + 0.5
(< 4.6(max))
-0.5 to +4.6
50
-55 to +125
-65 to +150
U
NIT
V
V
mA
°C
°C
T
ABLE
2. R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
S
YMBOL
M
IN
M
AX
1,2
V
CC
, V
CCQ
3.0
3.6
3
V
SS
, V
SSQ
0
0
1,4
Input High Voltage
V
IH
2.0
V
CC
+ 0.3
1,5
Input Low Voltage
V
IL
-0.3
0.8
1. All voltage referred to VSS
2. The supply voltage with all
V
CC
and V
CCQ
pins must be on the same level
3. The supply voltage with all V
SS
and V
SSQ
pins must be on the same level
4.
5.
V
IH
(max) =
V
CC
+2.0V for pulse width
<3ns
at
V
CC
V
IL
(min) =
V
SS
-2.0V for pulse width
<3ns
at
V
SS
P
ARAMETER
Supply Voltage
U
NIT
V
V
V
V
Memory
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
D
ESCRIPTION
Operating Current
Power Down Standby Current
V
ARIATION1
±10%
±10%
±10%
Active Standby Current
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
1.
±10% of value specified in Table 4
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Operating Current
1,2,3
S
YMBOL
I
CC1
T
EST
C
ONDITIONS
Burst length CAS Latency = 2
=1
CAS Latency = 3
t
RC
= min
CKE = V
IL
t
CK
= 12 ns
CKE = V
IL
t
CK
= 0
S
UBGROUPS
1, 2, 3
M
IN
M
AX
690
690
1, 2, 3
1, 2, 3
18
12
mA
mA
U
NITS
mA
Standby Current in Power Down
4
Standby Current in Power Down
( input signal stable)
5
I
CC2P
I
CC2PS
02.04.05 Rev 3
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
97SD3248
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
660
870
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-3
-6
-1.5
2.4
1320
18
3
6
1.5
mA
mA
uA
uA
uA
V
M
IN
M
AX
120
54
24
18
180
90
U
NITS
mA
mA
mA
mA
mA
mA
mA
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Standby Current in non power down
6
Standby Current in non power down
7
( Input signal stable)
Active standby current in
1,2,4
power down
Active standby current in power down
(input signal stable)
2,5
Active standby power in non power
down
1,2,6
Active standby current in non power
down ( input signal stable)
2,7
Burst Operating Current
1,2,8
CAS Latency = 2
CAS Latency = 3
Refresh Current
3
Self Refresh current
9,10
Input Leakage Current - CLK
Input Leakage Current - All Other
Output Leakage Current
Output high voltage
S
YMBOL
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
T
EST
C
ONDITIONS
CKE, CS = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
CKE = V
IL
t
CK
= 12 ns
CKE = V
IL
t
CK
= 0
CKE, CS1-6 = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
t
CK
= min
BL = 4
t
RC
= min
V
IH
>V
CC
- 0.2V
V
IL
< 0.2 V
0<V
LI
<V
CC
0<V
LI
<V
CC
0<V
LO
<V
CC
I
OH
= -4mA
Memory
I
CC5
I
CC6
I
LI
I
LI
I
LO
V
OH
I
OL
= 4 mA
1, 2, 3
0.4
V
Output low voltage
V
OL
1. I
CC1
depends on output load conditions when the device is selected. I
CC1
(max) is specified with the output open.
2. One Bank Operation
3. Input signals are changed once per clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals for V
IH
or V
IL
are fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current.
10.Use Self Refresh for temperatures less than 70
°C O
NLY
.
02.04.05 Rev 3
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
T
ABLE
5. AC Electrical Characteristics
97SD3248
M
IN
10
7.5
T
YPICAL
M
AX
U
NIT
ns
(V
CC
=3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
System clock cycle time
1
(CAS latency = 2)
(CAS latency = 3)
CLK high pulse width
1,7
CLK low pulse width
1,7,
Access time from CLK
1,2
(CAS latency = 2)
(CAS latency = 3)
Data-out hold time
1,2,3
CLK to Data-out low impedance
1,2,3,7
CLK to Data-out high impedance
1,47,
(CAS latency = 2, 3)
Input setup time
1,5,6
CKE setup time for power down exit
1
Input hold time
1,6
Ref/Active to Ref/Active command period
1
Active to Precharge command period
1
Active command to column command
1
(same bank)
Precharge to Active command period
1
Write recovery or data-in to precharge lead time
1
Active( a) to Active (b) command period
1
Transition time(rise and fall)
7
Refresh Period
S
YMBOL
t
CK
S
UBGROUPS
9, 10, 11
t
CKH
t
CKL
t
AC
9, 10, 11
9, 10, 11
9, 10, 11
2.5
2.5
6
6
ns
ns
ns
t
OH
t
LZ
t
HZ
t
AS
, t
CS,
t
DS
, t
CES
t
CESP
t
AH
, t
CH
, t
DH
t
CEH
t
RC
t
RAS
t
RCD
t
RP
t
DPL
t
RRD
t
T
t
REF
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
@ 105 °C
@ 85 °C
2.7
2
5.4
1.5
1.5
1.5
70
50
20
20
20
20
1
16
32
64
5
6.4
16
8
120000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Memory
@ 70 °C
128
1. AC measurement assumes t
T
=1ns. Reference level for timing of input signals is 1.5V.
2. Access time is measured at 1.5V.
3. t
LZ
(min) definesthe time at which the outputs achieve the low impedance state.
4. t
HZ
(min) defines the time at which the outputs achieve the high impedance state.
5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.
6. t
AS
/t
AH
: Address, t
CS
/t
CH
: /RAS, /CAS, /WE, DQM
7. Guarenteed by design (Not tested).
8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)
02.04.05 Rev 3
All data sheets are subject to change without notice
5
©2005 Maxwell Technologies
All rights reserved.
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