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www.fairchildsemi.com
FAN5059
High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms
Features
• P
rogrammable output for Vcore from 1.3V to 3.5V using
an integrated 5-bit DAC
• Controls adjustable linears for Vagp (selectable 1.5V/3.3V),
Vclock (2.5V), and Vtt (1.5V) or Vnorthbridge (1.8V)
• Meets VRM specification with as few as 5 capacitors
• Meets 1.550V +40/-70mV over initial tolerance,
temperature and transients
•
•
•
•
•
•
•
Remote sense
Programmable Active Droop™ (Voltage Positioning)
Drives N-Channel MOSFETs
Overcurrent protection using MOSFET sensing
85% efficiency typical at full load
Integrated Power Good and Enable/Soft Start functions
24 pin SOIC package
Applications
•
•
•
•
Power supply for Pentium
®
III Camino Platform
Power supply for Pentium III Whitney Platform
VRM for Pentium III processor
Programmable multi-output power supply
Description
The FAN5059 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Camino,
and provides a complete solution for the Intel Whitney and other
high-performance processors. The FAN5059 features remote
voltage sensing, independently adjustable current limit, and a
proprietary Programmable Active Droop
™
for optimal converter
transient response. The FAN5059 uses a 5-bit D/A converter
to program the output voltage from 1.3V to 3.5V. The
FAN5059 uses a high level of integration to deliver load
Block Diagram
+3.3V
9
10
VCCP
11
+
-
+
-
+5V
VCCA 21
REF
PWRGD,
OCL
OCL
REF
+12V
PWRGD,
OCL
OSC
-
+
15
14
13
3.3/1.5V
5-Bit
DAC
8 7 65 4
VID0 VID2 VID4
VID1 VID3
1.24V
Reference
3
GNDA
16
ENABLE/SS
Power
Good
-
+
-
+
18
R
S
20
24 VCCP
1 HIDRV
+5V
-
+
19
R
D
+1.5V
12
+2.5V
Digital
Control
2
VCC
+
-
V
PWRGD, OCL
-
+
23 LODRV
22
GNDP
17
PWRGD
Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.
Rev. 1.0.0
FAN5059
PRODUCT SPECIFICATION
currents in excess of 16A from a 5V source with minimal
external circuitry. Synchronous-mode operation offers opti-
mum efficiency over the entire specified output voltage range.
An on-board precision low TC reference achieves tight toler-
ance voltage regulation without expensive external compo-
nents, while Programmable Active Droop
™
permits exact
tailoring of voltage for the most demanding load transients. The
FAN5059 includes linear regulator controllers for Vtt termina-
tion (1.5V), Vclock (2.5V), and Vnorthbridge (1.8V) or Vagp
(selectable 1.5V/3.3V), each adjustable with an external divider.
The FAN5059 also offers integrated functions including Power
Good, Output Enable/Soft Start and current limiting, and is
available in a 24 pin SOIC package.
Pin Assignments
HIDRV
SW
GNDA
VID4
VID3
VID2
VID1
VID0
VTTGATE
VTTFB
VCKGATE
VCKFB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB
FAN5059
Pin Definitions
Pin
Number Pin Name
1
2
3
4-8
HIDRV
SW
GNDA
VID0-4
Pin Function Description
High Side FET Driver.
Connect this pin through a resistor to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5".
High side Driver Source and Low side Driver Drain Switching Node.
Together with
DROOP and ILIM pins allows FET sensing for Vcc current.
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
Voltage Identification Code Inputs.
These open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 2. Pull-up resistors are
internal to the controller.
Gate Driver for VTT Transistor.
For 1.5V output.
Voltage Feedback for VTT.
Gate Driver for VCK Transistor.
For 2.5V output.
Voltage Feedback for VCK.
Voltage Feedback for VAGP.
Gate Driver for VAGP Transistor.
For 3.3/1.5V output.
Type Detect.
Sets 3.3V or 1.5V for AGP.
Output Enable.
A logic LOW on this pin will disable all outputs. An internal current source
allows for open collector control. This pin also doubles as soft start for all outputs.
Power Good Flag.
An open collector output that will be logic LOW if any output voltage
is more than ±12% outside of the nominal output voltage setpoint.
Vcc Current Feedback.
Pin 18 is used in conjunction with pin 2 as the input for the Vcc
current feedback control loop. Layout of these traces is critical to system performance.
See Application Information for details.
Droop set.
Use this pin to set magnitude of active droop.
Vcc Voltage Feedback.
Pin 20 is used as the input for the Vcc voltage feedback control
loop. See Application Information for details regarding correct layout.
Analog VCC.
Connect to system 5V supply and decouple with a 0.1µF ceramic capacitor.
Power Ground.
Return pin for high currents flowing in pin 24 (VCCP).
Vcc Low Side FET Driver.
Connect this pin through a resistor to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should
be <0.5".
Power VCC.
For all FET drivers. Connect to system 12V supply through a 33
Ω
, and
decouple with a 1µF ceramic capacitor.
9
10
11
12
13
14
15
16
17
18
VTTGATE
VTTFB
VCKGATE
VCKFB
VAGPFB
VAGPGATE
TYPEDET
ENABLE/SS
PWRGD
ILIM
19
20
21
22
23
DROOP
VFB
VCCA
GNDP
LODRV
24
VCCP
2
REV. 1.0.0 7/13/00
PRODUCT SPECIFICATION
FAN5059
Absolute Maximum Ratings
Supply Voltage VCCA to GND
Supply Voltage VCCP to GND
Voltage Identification Code Inputs, VID0-VID4
All Other Pins
Junction Temperature, T
J
Storage Temperature
Lead Soldering Temperature, 10 seconds
Thermal Resistance Junction-to-ambient,
Θ
JA1
Note:
1. Component mounted on demo board in free air.
13.5V
15V
VCCA
13.5V
150°C
-65 to 150°C
300°C
75°C/W
Recommended Operating Conditions
Parameter
Supply Voltage VCCA
Input Logic HIGH
Input Logic LOW
Ambient Operating Temperature
Output Driver Supply, VCCP
0
10.8
12
Conditions
Min.
4.5
2.0
0.8
70
13.2
Typ.
5
Max.
5.25
Units
V
V
V
°C
V
Electrical Specifications
(V
CCA
= 5V, V
CCP
= 12V, V
OUT
= 2.0V, and T
A
= +25°C using circuit in Figure 1 unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
VCC Regulator
Output Voltage
Output Current
Initial Voltage Setpoint
I
LOAD
= 0.8A,V
OUT
= 2.400V
V
OUT
= 2.000V
V
OUT
= 1.550V
T
A
= 0 to 70°C,V
OUT
= 2.000V
V
OUT
= 1.550V
V
IN
= 4.75V to 5.25V
I
LOAD
= 0.8A to 12.5A
20MHz BW, I
LOAD
= 18A
V
OUT
= 2.000V
V
OUT
= 1.550V
3
I
LOAD
= 0.8A to 18A, V
OUT
= 2.000V
V
OUT
= 1.550V
3
I
LOAD
= 18A, V
OUT
= 2.0V
See Figure 3
See Figure 3
•
•
•
•
•
1.940
1.480
1.900
1.480
45
50
85
50
50
•
•
•
13.0
2.397
2.000
1.550
See Table 1
•
1.3
18
2.424
2.020
1.565
+8
+6
-4
14.4
60
11
2.070
1.590
2.100
1.590
60
15.8
2.454
2.040
1.580
3.5
V
A
V
V
V
mV
mV
mV/V
K
Ω
mV
mVpk
V
V
µA
%
nsec
nsec
Conditions
Min.
Typ.
Max.
Units
Output Temperature Drift
Line Regulation
Internal Droop Impedance
Maximum Droop
Output Ripple
Total Output Variation,
Steady State
1
Total Output Variation,
Transient
2
Short Circuit Detect Current
Efficiency
Output Driver Rise & Fall Time
Output Driver Deadtime
REV. 1.0.0 7/13/00
3
FAN5059
PRODUCT SPECIFICATION
Electrical Specifications
(Continued)
(V
CCA
= 5V, V
CCP
= 12V, V
OUT
= 2.0V, and T
A
= +25°C using circuit in Figure 1 unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Duty Cycle
5V UVLO
12V UVLO
Soft Start Current
VTT Linear Regulator
Output Voltage
Under Voltage Trip Level
VCLK Linear Regulator
Output Voltage
Under Voltage Trip Level
VAGP Linear Regulator
Output Voltage
Output Voltage
Under Voltage Trip Level
Common Functions
Oscillator Frequency
PWRGD Threshold
Logic HIGH, All Outputs
Logic LOW, Any Output
•
•
•
255
88
84
30
310
345
112
116
kHz
%V
OUT
µsec
I
LOAD
≤
2A, TYPEDET=0V
I
LOAD
≤
2A, TYPEDET=OPEN
Over Current
•
•
1.425
3.135
1.5
3.3
80
1.575
3.465
V
V
%V
O
I
LOAD
≤
2A
Over Current
•
2.375
2.5
80
2.625
V
%V
O
I
LOAD
≤
2A
Over Current
•
1.455
1.5
80
1.545
V
%V
O
•
•
•
Conditions
Min.
0
3.74
7.65
5
4
8.5
10
Typ.
Max.
100
4.26
9.35
17
Units
%
V
V
µA
Linear Regulator Under Voltage Over Current
Delay Time
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is
measured at the converter’s VFB sense point.
2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5m
Ω
trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s VRM 8.4
specification of +50, –80mV. If Intel specifications on maximum plane resistance from the converter’s output capacitors to the CPU
are met, the specification of +40, –70mV at the capacitors will also be met.
4
REV. 1.0.0 7/13/00
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