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G65SC112ACS-3

Description
Microprocessor, 8-Bit, 3MHz, CMOS, CDIP40, CERAMIC, DIP-40
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size702KB,13 Pages
ManufacturerCalifornia Micro Devices
Download Datasheet Parametric View All

G65SC112ACS-3 Overview

Microprocessor, 8-Bit, 3MHz, CMOS, CDIP40, CERAMIC, DIP-40

G65SC112ACS-3 Parametric

Parameter NameAttribute value
MakerCalifornia Micro Devices
Parts packaging codeDIP
package instructionDIP,
Contacts40
Reach Compliance Codeunknown
Address bus width16
bit size8
boundary scanNO
External data bus width8
FormatFIXED POINT
Integrated cacheNO
JESD-30 codeR-CDIP-T40
low power modeNO
Number of terminals40
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Certification statusNot Qualified
Maximum seat height5.72 mm
speed3 MHz
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width15.24 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR
Base Number Matches1
AP216
© 2000 California Micro Devices Corp. All rights reserved.
C0261100A
215 Topaz Street, Milpitas, California 95035

11/06/2000
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
Can anyone explain why the value is set like this? Thank you!!! (marked in red)
#include "hall.h" unsigned char FaultF=0;//fault flagunsigned char Run_dir=1;//running direction, 0-1 oppositeunsigned char bHallStartStep; unsigned int OutPwmValue=0; unsigned char bHallSteps[2][8]={...
KCP stm32/stm8
Can G2553 accurately time to microseconds?
1. Can G2553 accurately time the device to the microsecond? What can I do? How to debug the precise timing problem of DS18B20???...
xiaohengyan Microcontroller MCU
Source synchronous timing issues
Many ASIC peripherals now use DDR (II) SDRAM (SRAM). Due to the high data transmission rate, data signals are basically source synchronous. Many timing materials believe that there is no length limit ...
eeleader FPGA/CPLD
Digitally controlled power supply using DSP for secondary voltage regulation
[[i] This post was last edited by lrz123 on 2011-10-25 10:48[/i]]...
lrz123 DIY/Open Source Hardware
About the digital tube display problem
I have been using FPGA to make a digital clock these days, using six digital tubes for display. I used a 20M crystal oscillator and divided it to get a 1KHZ signal, and used this signal to scan the bi...
gavin_8724 FPGA/CPLD

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