MwT-H7
28
GHz Medium Power/ High Gain
AlGaAs/InGaAs PHEMT
DOWNLOAD ADDITIONAL DATA
WWW.MWTINC.COM
All Dimensions in Microns
50
70
241
100
50 50
356
CHIP THICKNESS = 125 MICRONS
50
50
FEATURES
•
21.5 dBm POWER OUTPUT AT 12 GHz
•
EXCELLENT FOR HIGH GAIN AND MEDIUM POWER
APPLICATIONS
•
0.3 MICRON REFRACTORY METAL/GOLD GATE
•
250 MICRON GATE WIDTH
•
CHOICE OF CHIP AND TWO PACKAGE TYPES
50
DESCRIPTION
The MwT-H7 is an AlGaAs/InGaAs heterojunction
PHEMT
(Pseudomorphic-High-Electron-Mobility Transistor) device whose nominal 0.3
micron gate length and 250 micron gate width make it ideally suited to applications requiring high-gain and medium power in the 500
MHz to
28
GHz frequency range. The device is equally effective for either wideband (e.g. 6-18 GHz) or narrow-band applications. The
chip is produced using MwT’s reliable metal system and all devices are screened to insure reliability. All chips are passivated using MwT’s
patented “Diamond-Like Carbon” process for increased durability.
DC SPECIFICATIONS AT Ta = 25
°
C
SYMBOL
PARAM. & CONDITIONS
UNITS
MIN
TYP
MAX
RF SPECIFICATIONS AT Ta = 25
°
C
SYMBOL
PARAMETERS AND CONDITIONS
FREQ
UNITS
MIN
TYP
IDSS
Gm
Vp
BVGSO
BVGDO
Rth
Saturated Drain Current
Vds= 3.0 V VGS= 0.0 V
Transconductance
Vds= 3.0 V VGS= 0.0 V
Pinch-off Voltage
Vds= 3.0 V IDS= 1.0 mA
Gate-to-Source Breakdown Volt.
Igs= -0.4mA, Igd= 0
Gate-to-Drain Breakdown Volt.
Igd= -0.4 mA, Igs= 0
Thermal
MwT-H7 Chip
Resistance
MwT -H770, H773
mA
mS
V
V
V
°C/W
34
50
75
-1.5
-5.0
-6.0
-8.0
-8.0
106
P1dB
SSG
Output Power at 1 dB Compression
VDS= 5.0 V Idss= 50mA IDS=0.8
Small Signal Gain
VDS= 5.0 V Idss= 50mA IDS=0.8
Optimum Noise Figure
VDS= 3.0 V IDS= 10mA
Gain at Optimum Noise Figure
VDS= 3.0 V IDS= 10mA
Recommended IDSS Range
for Optimum P1dB
12 GHz
dBm
dB
dB
%
mA
20.0
11.0
21.5
12.0
2.0
10.0
50-
86
12 GHz
12 GHz
12 GHz
-5.0
NFopt
GA
Idss
180-
380
DEVICE EQUIVALENT CIRCUIT MODEL
PARAMETER
Source Resistance
Source Inductance
Drain-Source Resistance
Drain-Source Capacitance
Drain Resistance
Drain Pad Capacitance
Drain Inductance
Gate Bond Wire Inductance
Gate Pad Capacitance
Gate Resistance
Gate-Source Capacitance
Channel Resistance
Gate-Drain Capacitance
Transconductance
Transit Time
Rs
Ls
Rds
Cds
Rd
Cpd
Ld
Lg
Cpg
Rg
Cgs
Ri
Cgd
gm
tau
VALUE
2.6
0.025
400.0
0.070
3.67
0.027
0.159
0.089
0.050
0.20
0.4
6.9
0.04
85.0
3.02
Ω
nH
Ω
pF
Ω
pF
nH
nH
pF
Ω
pF
Ω
pF
mS
psec
Lg
GATE
Rg
Cgs
Cgd
Rds
Rd
Ld
DRAIN
Cpg
Ri
gm
tau
Rs
Ls
SOURCE
Cds
Cpd
ORDERING INFORMATION
Chip
Package 70
Package 73
MwT-H7
MwT-H770
MwT-H773
NOTE:
For Package information, please see the Fapp0002 note from our website at www.mwtinc.com.
When placing order or inquiring, please specify BIN range, wafer no., if known, and screening
level required.
4268 Solar Way
Fremont California 94538 Phone: (510) 651-6700 Fax: (510) 651-2208
All rights reserved. MicroWave Technology, Inc. All specifications subject to change without notice.
MwT-H7
32 GHz Medium Power/ High Gain
AlGaAs/InGaAs PHEMT
MwT-H7
DUAL BIAS
50
Ω
Output
Microstrip
2 Mils
MwT-H7
OPTIONAL BONDING
50
Ω
Output
Microstrip
2 Mils
Output Reference
Plane
19 Mils Long
Copper Heat Sink
5 Mils Below Level of
Microstrip
Output Reference
Plane
19 Mils Long
Copper Heat Sink
5 Mils Below Level of Microstrip
MwT
FPH7
20 Mils
MwT
FPH7
20 Mils
7 Mils Long
Input Reference
Plane
50
Ω
Input
Microstrip
2 Mils
All Bond
Wires are 1.0
Mil Diameter
Gold Ridge
5x33x5 Mils
(2 each)
7 Mils Long
Input Reference
Plane
50
Ω
Input
Microstrip
2 Mils
Gold Blocks
10x10x5 for
Dual Bias, or
25 pF Caps
for Single
Bias (2 each)
Bonding Configuration used to Obtain “S” Data
All Bond
Wires are 1.0
Mil Diameter
SAFE OPERATING LIMITS vs. BACKSIDE CHIP
150
150 125 100
75°
C or Lower
°
Absolute Maximum
Continuous Maximum
MAXIMUM RATINGS AT Ta = 25
°
C
100
Ids (mA)
125
100
75°
C or Lower
°
SYMBOL
PARAMETER
UNITS
CONT MAX
1
ABSOLUTE MAX
2
50
VDS
Tch
Tst
Pin
Drain to Source Voltage
Channel Temperature
Storage Temperature
RF Input Power
V
°
C
°
C
mW
See Safe Operating Limits
+150
+175
-65 to +150
+175
80
120
25
0
0
2
4
Vds (V)
6
8
NOTES: 1. Exceeding any one of these limits in continuous operation may reduce the
mean-time-to-failure below the design goals.
2. Exceeding any one of these limits may cause permanent damage.
BIN SELECTION
BIN#
IDSS
(mA)
1
34-
38
2
38-
42
3
42-
46
4
46-
50
5
50-
54
6
54-
58
7
58-
62
8
62-
66
9
66-
70
10
70-
74
11
74-
78
12
78-
82
13
82-
86
14
86-
90
14
90-
94
14
94-
98
BIN ACCURACY STATEMENT
When placing order or inquiring, please specify BIN range, wafer no., if known, and screening level required.
For more information on device handling, bin accuracy, or bin selection please see Fapp0001 on our website.
4268 Solar Way
Fremont
California 94538 Phone: (510) 651-6700 Fax: (510) 651-2208
All rights reserved. MicroWave Technology, Inc. All specifications subject to change without notice.
Embedded System
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