TS 68040
THIRD-GENERATION
32-BIT MICROPROCESSOR
DESCRIPTION
The TS 68040 is Thomson’s third generation of 68000-com-
patible, high-performance, 32-bit microprocessors. The
TS 68040 is a virtual memory microprocessor employing mul-
tiple, concurrent execution units and a highly integrated archi-
tecture to provide very high performance in a monolithic
HCMOS device. On a single chip, the TS 68040 integrates an
68030-compatible integer unit, an IEEE 754-compatible floa-
ting-point unit (FPU), and fully independent instruction and
data demand-paged memory management units (MMUs), in-
cluding independent 4K-byte instruction and data caches. A
high degree of instruction execution parallelism is achieved
through the use of multiple independent execution pipelines,
multiple internal buses, and a full internal Harvard architec-
ture, including separate physical caches for both instruction
and data accesses. The TS 68040 also directly supports ca-
che coherency in multimaster applications with dedicated on-
chip bus snooping logic.
The TS 68040 is user-object-code compatible with previous
members of the TS 68000 Family and is specifically opti-
mized to reduce the execution time of compiler-generated
code. The 68040 HCMOS technology, provides an ideal ba-
lance between speed, power, and physical device size.
Figure 1 is a simplified block diagram of the TS 68040. Ins-
truction execution is pipelined in both the integer unit and FPU.
Independent data and instruction MMUs control the main ca-
ches and the address translation caches (ATCs). The ATCs
speed up logical-to-physical address translations by storing re-
cently used translations. The bus snooper circuit ensures cache
coherency in multimaster and multiprocessing applications.
MAIN FEATURES
26-42 MIPS integer performance.
3.5-5.6 MFLOPS floating-point-performance.
IEEE 754-Compatible FPU.
Independant instruction and data MMUs.
4K-byte physical instruction cache and 4K-byte physical
data cache accessed simultaneously.
32-bit, nonmultiplexed external address and data buses
with synchronous interface.
User-object-code compatibility with all earlier TS 68000
microprocessors.
Multimaster / multiprocessor support via bus snooping.
Concurrent integer unit, FPU, MMU, bus controller, and
bus snooper maximize throughput.
4-Gbyte direct addressing range.
Software support including optimizing C compiler and
unix* system V port.
IEEE P 1149-1 test mode (J tag).
f = 25 MHz, 33 MHz ; V CC = 5 V
±
5 % ; PD = 7 W.
The use of the TS 88915T clock driver is suggested.
SCREENING
MIL-STD-883.
DESC. Drawing 5962-93143.
TCS standards.
R suffix
PGA 179
Ceramic Pin Grid Array
Cavity down
F suffix
CQFP 196
Gullwing shape lead Ceramic Quad Flat Pack
This document contains information on a new product. Specifica-
tions and information herein are subject to change without notice.
February 1998
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TS 68040
SUMMARY
A - GENERAL DESCRIPTION
1 - INTRODUCTION
2 - PIN ASSIGNMENTS
2.1 - PGA 179
2.2 - CQFP 196
B - DETAILED SPECIFICATIONS
1 - SCOPE
2 - APPLICABLE DOCUMENTS
3 - REQUIREMENTS
3.1 - General
3.2 - Design and construction
3.2.1 - Terminal connections
3.2.2 - Lead material and finish
3.2.3 - Package
3.3 - Electrical characteristics
3.3.1 - Absolute maximum rating
3.3.2 - Recommended condition of use
3.4 - Thermal consideration
3.4.1 - General thermal consideration
3.4.2 - Thermal characteristics
3.5 - Mechanical and environment
3.6 - Marking
3 - SIGNAL DESCRIPTION
4 - QUALITY CONFORMANCE
4 -
INSPECTION
4.1 - DESC / MIL-STD-883
5 - ELECTRICAL CHARACTERISTICS
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
6.5
6.5
6.7
-
-
-
-
-
-
-
-
-
-
-
General requirements
Static characteristics
Dynamic characteristics
Switching test circuit and waveforms
Programming model
Data types and addressing modes
Instruction set overview
Instruction and data caches
Operand transfer mechanism
Exception processing
Memory management units
6 - FUNCTIONAL DESCRIPTION
7 - PREPARATION FOR DELIVERY
7.1 - Packaging
7.2 - Certificate of compliance
8 - HANDLING
9 - PACKAGE MECHANICAL DATA
9.1 - 179 pins - PGA
9.2 - 196 pins - Tie bar CQFP
9.3 - 196 pins - Gullwing CQFP
10 - ORDERING INFORMATION
10.1 - MIL-STD-883 C
10.2 - DESC Drawing 5962-93143.
10.3 - Detailed TS 68040 part list
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TS 68040
A - GENERAL DESCRIPTION
Figure 1 :
Block diagram.
1 - INTRODUCTION
The TS 68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the
TS 68030 microprocessor with independent 4K-byte data and instruction caches and an on-chip FPU. The TS 68040 maintains
the 32-bit registers available with the entire TS 68000 Family as well as the 32-bit address and data paths, rich instruction
set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU
operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments.
The TS 68040 FPU is user-object-code compatible with the TS 68882 floating-point coprocessor and conforms to the
ANSI / IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly
used subset of the TS 68882 instruction set, and includes additional instruction formats for single and double-precision
rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit.
The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using
translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When
an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and
the physical address is supplied immediately, incurring no delay for adress translation. Each MMU has two transparent
translation registers available that define a one-to-one mapping for adress space segments ranging in size from 16 Mbytes
to 4 Gbytes each.
Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated
address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address
spaces protect the integrity of independent processes.
The instruction and data caches operate independently from the rest of the machine, storing information for fast access by
the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access
to both. The data cache provides writethrough or copyback write modes that can be configured on a page-by-page basis.
The TS 68040 bus controller supports a high-speed, nonmultiplexed, synchronous external bus interface, which allows the
following transfer sizes : byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using
burst transfers for both reads and writes to provide high data transfer rates.
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TS 68040
2 - PIN ASSIGNMENTS
2.1 - PGA 179
Figure 2 :
Bottom view.
Table 1
GND
PLL
Internal logic
C6, C7, C9, C11, C13, K3, K16, L3,
M16, R4, R11, R13, S10, T4, S9, R6,
R10
B2, B4, B6, B8, B10, B13, B15, B17,
D2, D17, F2, F17, H2, H17, L2, L17,
N2, N17, Q2, Q17, S2, S15, S17
S8
C5, C8, C10, C12, C14, H3, H16, J3,
J16, L16, M3, R5, R12, R8
B5, B9, B14, C2, C17, G2, G17, M2,
M17, R2, R17, S16
VCC
Output drivers
4/38
TS 68040
2.2 - CQFP 196
Figure 3 :
Pin assignments.
Table 2
GND
PLL
Internal logic
4, 9, 10, 19, 32, 45, 73, 88, 113, 119,
121, 122, 124, 125, 129, 130, 141, 159,
172
7, 15, 22, 28, 35, 42, 49, 50, 51, 57,
63, 69, 76, 77, 83, 84, 91, 97, 98, 99,
105, 106, 146, 147, 148, 149, 155, 162,
163, 169, 176, 182, 183, 189, 195, 196
127
3, 18, 31, 40, 46, 60, 72, 87, 114, 126,
137, 158, 173, 186
VCC
Output drivers
12, 25, 38, 54, 66, 80, 94, 102, 152,
166, 179, 192
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