or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1006
Introduction_01.5
Lattice Semiconductor
Introduction
LatticeECP2/M Family Data Sheet
Table 1-1. LatticeECP2 (including “S-Series”) Family Selection Guide
Device
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
ECP2-6
ECP2-12
ECP2-20
402
ECP2-35
450
ECP2-50
500
ECP2-70
500
583
Table 1-2. LatticeECP2M (including “S-Series”) Family Selection Guide
Device
LUTs (K)
sysMEM Blocks (18kb)
Embedded Memory (Kbits)
Distributed Memory (Kbits)
sysDSP Blocks
18x18 Multipliers
GPLL+SPLL+DLL
Maximum Available I/O
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1152-ball fpBGA (35 x 35 mm)
1156-ball fpBGA (35 x 35 mm)
ECP2M20
19
66
1217
41
6
24
2+6+2
304
4 / 140
4 / 304
ECP2M35
34
114
2101
71
8
32
2+6+2
410
4 / 140
4 / 303
4 / 410
4 / 270
8 / 372
8 / 410
16 / 416
16 / 430
16 / 416
16 / 520
16 / 616
ECP2M50
48
225
4147
101
22
88
2+6+2
410
ECP2M70
67
246
4534
145
24
96
2+6+2
430
ECP2M100
95
288
5308
202
42
168
2+6+2
616
Packages and SERDES / I/O Combinations
Introduction
The LatticeECP2/M family of FPGA devices has been optimized to deliver high performance features such as
advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous inter-
faces in an economical FPGA fabric. This combination was achieved through advances in device architecture and
the use of 90nm technology.
The LatticeECP2/M FPGA fabric was optimized for the new technology from the outset with high performance and
low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Analogue and Mixed Signal
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