MCM63R836AFC3.7R datasheet, PDF

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MCM63R836AFC3.7R: Description256KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119; Categorystorage storage; File Size141KB，21 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM63R836AFC3.7R Overview

256KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

MCM63R836AFC3.7R Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	1.85 ns
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	LATE-WRITE SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.77 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63R836A/D

8M Late Write HSTL

The MCM63R836A/918A is an 8M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM63R918A

(organized as 512K words by 18 bits) and the MCM63R836A (organized as

256K words by 36 bits) are fabricated in Motorola’s high performance silicon gate

copper CMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

the RAM. At the rising edge of CK, all addresses, write enables, and synchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control

signals. Read data is also driven on the rising edge of CK.

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)

and output voltage (V DDQ ) gives the system designer greater flexibility in

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or

the entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

2.5 V – 5% to 3.3 V + 10% Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM63R836A / 918A–3.0 = 3.0 ns

MCM63R836A / 918A–3.3 = 3.3 ns

MCM63R836A / 918A–3.7 = 3.7 ns

MCM63R836A / 918A–4.0 = 4.0 ns

•

Sleep Mode Operation (ZZ pin)

•

119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic

Ball Grid Array (PBGA)

MCM63R836A

MCM63R918A

FC PACKAGE

PBGA

CASE 999D–01

10/16/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM63R836A•MCM63R918A

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