FUJITSU SEMICONDUCTOR
DATA SHEET
AE0.2E
FLASH MEMORY
CMOS
8 M (1 M
×
8/512 K
×
16) BIT
MBM29SL800TE/BE
-90/10
s
DESCRIPTION
The MBM29SL800TE/BE are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TE/BE are offered in a 48-ball FBGA and xx-ball SCSP packages.
These devices are designed to be programmed in-system with the standard system 1.8 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
(Continued)
s
PRODUCT LINE UP
Part No.
V
CC
Max Address Access Time
Max CE Access Time
Max OE Access Time
90ns
90ns
30ns
MBM29SL800TE/BE-90
MBM29SL800TE/BE-10
100ns
100ns
35ns
1.65V to 1.95V
s
PACKAGE
48-pin Plastic FBGA
48-pin Plastic SCSP
(BGA-48P-M××)
(WLP-××P-M××)
MBM29SL800TE/BE
-90/10
(Continued)
The standard MBM29SL800TE/BE offer access times 90 ns and 100 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE)
, write enable (WE) , and output enable (OE) controls.
The device supports pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify
proper cell margin.
Each sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL800TE/BE are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally returns to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29SL800TE/BE memories electrically erase the
entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are pro-
grammed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
2 (AE0.2E) Advance Info.
MBM29SL800TE/BE
-90/10
s
FEATURES
•
0.23
µ
m Process Technology
•
Single 1.8 V read, program, and erase
Minimizes system level power requirements
•
Compatible with JEDEC-standard world-wide pinouts
48-ball FBGA (Package suffix : PBT)
xx-ball SCSP (Package suffix : PW)
•
Minimum 100,000 program/erase cycles
•
High performance
90 ns maximum access time
•
Sector erase architecture
One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
•
Boot Code Sector Architecture
T
=
Top sector
B
=
Bottom sector
•
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready/Busy output
(RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
•
Sector protection
Hardware method disables any combination of sectors from program or erase operations
•
Sector Protection set function by Extended sector Protect command
• Fast programming Function by Extended Command
•
Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
Advance Info. (AE0.2E) 3
MBM29SL800TE/BE
-90/10
s
PIN ASSIGNMENTS
FBGA
(TOP VIEW)
Marking side
A6
A
13
A5
A
9
A4
B6
A
12
B5
A
8
B4
C6
A
14
C5
A
10
C4
D6
A
15
D5
A
11
D4
N.C.
D3
N.C.
D2
A
5
D1
A
1
E6
A
16
E5
DQ
7
E4
DQ
5
E3
DQ
2
E2
DQ
0
E1
A
0
F6
G6
H6
BYTE DQ
15
/A
-1
V
SS
F5
DQ
14
F4
DQ
12
F3
DQ
10
F2
DQ
8
F1
CE
G5
DQ
13
G4
V
CC
G3
DQ
11
G2
DQ
9
G1
OE
H5
DQ
6
H4
DQ
4
H3
DQ
3
H2
DQ
1
H1
V
SS
WE RESET N.C.
A3
RY/BY
A2
A
7
A1
A
3
B3
N.C.
B2
A
17
B1
A
4
C3
A
18
C2
A
6
C1
A
2
(BGA-48P-M××)
SCSP*
(TOP VIEW)
Marking side
TBD
(WLP-××P-M××)
*: NOTICE: The backside of device silicon substrate is exposed to the marking side of device package.
This portion has lower strength against the mechanical stress than the standard plastic mold package,
which requires to be careful in mechanical handling. Also, the exposed backside of silicon has electrical
potential of device substrate, and needs to be kept out of contact with the external potential.
4 (AE0.2E) Advance Info.
MBM29SL800TE/BE
-90/10
s
PIN DESCRIPTION
Table 1
Pin name
A
18
to A
0
, A-
1
DQ
15
to DQ
0
CE
OE
WE
RESET
RY/BY
BYTE
V
CC
V
SS
N.C.
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Hardware Reset Pin/Temporary Sector Unprotection
Ready/Busy Output
Selects 8-bit or 16-bit mode
Device Power Supply
Device Ground
No Internal Connection
MBM29SL800TE/BE Pin Configuration
Function
Advance Info. (AE0.2E) 5
NXP MCU
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