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5962R9652601VCA

Description
NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size224KB,9 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962R9652601VCA Overview

NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

5962R9652601VCA Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-CDIP-T14
JESD-609 codee0
length19.43 mm
Logic integrated circuit typeNAND GATE
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)15 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose100k Rad(Si) V
width7.62 mm
Base Number Matches1
Standard Products
UT54ACS20/UT54ACTS20
Dual 4-Input NAND Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS20 - SMD 5962-96526
UT54ACTS20 - SMD 5962-96527
DESCRIPTION
The UT54ACS20 and the UT54ACTS20 are dual 4-input
NAND gates. The circuits perform the Boolean functions
Y = A⋅B⋅C⋅D or Y = A + B + C + D in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
L
X
X
X
B
H
X
L
X
X
C
H
X
X
L
X
D
H
X
X
X
L
OUTPUT
Y
L
H
H
H
H
PINOUTS
14-Pin DIP
Top View
A1
B1
NC
C1
D1
Y1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
D2
C2
NC
B2
A2
Y2
14-Lead Flatpack
Top View
A1
B1
NC
C1
D1
Y1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
D2
C2
NC
B2
A2
Y2
LOGIC DIAGRAM
A1
B1
C1
D1
A2
B2
C2
D2
Y1
LOGIC SYMBOL
A1
B1
C1
D1
A2
B2
C2
D2
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(8)
Y2
(6)
Y1
&
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
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