The UT54ACS02E is a quadruple, two-input NOR gate. The
circuit performs the Boolean functions
Y = A + B or Y = A
⋅
B in positive logic.
The device is characterized over the full military temperature
range of -55°C to +125°C.
PINOUT
14-Lead Flatpack
Top View
Y1
A1
B1
Y2
A2
B2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Y4
B4
A4
Y3
B3
A3
FUNCTION TABLE
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
L
L
H
LOGIC SYMBOL
A1 (2)
B1 (3)
A2 (5)
(6)
B2
(8)
A3
(9)
B3
(11)
A4
(12)
B4
≥1
(1)
(4)
(10)
(13)
Y1
Y2
LOGIC DIAGRAM
A1
Y3
Y4
B1
A2
B2
A3
B3
A4
Y1
Y2
Y3
Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
B4
1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+ .3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
Description
Low-level input voltage
1
High-level input voltage
1
CONDITION
VDD
3.0V
5.5V
V
IH
3.0V
5.5V
I
IN
V
OL
Input leakage current
Low-level output voltage
3
High-level output voltage
3
Short-circuit output current
2 ,4
V
IN
= V
DD
or V
SS
I
OL
= 100µA
5.5V
3.0V
4.5V
V
OH
I
OH
= -100µA
3.0V
4.5V
I
OS
V
O
= V
DD
and V
SS
3.0V
5.5V
I
OL
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
I
OH
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
P
total
I
DDQ
C
IN
C
OUT
Power dissipation
2, 8
Quiescent Supply Current
Input capacitance
5
Output capacitance
5
C
L
= 50pF
V
IN
= V
DD
or V
SS
ƒ
= 1MHz
ƒ
= 1MHz
3.0V
5.5V
3.0V
5.5V
5.5V
3.0V
5.5V
0V
0V
2.75
4.25
-100
-200
6
8
-6
-8
1.8
0.72
10
15
15
mW/
MHz
µA
pF
pF
mA
100
200
mA
mA
2.1
3.85
-1
1
0.25
0.25
V
µA
V
MIN
MAX
0.9
1.65
V
UNIT
V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power dissipation specified per switching output.
9. This value is guaranteed based on characterization data, but not tested.
3
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E
2
(V
DD
= 3.0V to 5.5V; V
SS
= 0V
1
, -55°C < T
C
< +125°C)
SYMBOL
t
PLH
PARAMETER
Input to Yn
CONDITION
C
L
= 30pF
V
DD
3.0V & 3.6V
4.5V & 5.5V
MINIMUM
1
1
1
1
1
1
1
1
MAXIMUM
11
7
15
11
13
9
17
13
UNIT
ns
C
L
= 50pF
3.0V & 3.6V
4.5V & 5.5V
ns
t
PHL
Input to Yn
C
L
= 30pF
3.0V & 3.6V
4.5V & 5.5V
ns
C
L
= 50pF
3.0V & 3.6V
4.5V & 5.5V
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
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