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5T940-30NLI8

Description
Low Skew Clock Driver, PQCC28
Categorylogic    logic   
File Size285KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

5T940-30NLI8 Overview

Low Skew Clock Driver, PQCC28

5T940-30NLI8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
ECCN codeEAR99
JESD-30 codeS-PQCC-N28
JESD-609 codee0
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCN
Encapsulate equivalent codeLCC28,.24SQ,25
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3 V
Certification statusNot Qualified
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formNO LEAD
Terminal pitch0.635 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Base Number Matches1
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on Q
OUT
• Regenerated input clock or Q
OUT
/4 on Q
REG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode 0: Q
OUT
range 155.5 - 166.6MHz. Q
REG
is a regenerated version
of the input clock.
- Mode 1: Q
OUT
range 622 - 666.5MHz. Q
REG
output 155.5-166.6MHz.
- Mode 2: Q
OUT
range 622 - 666.5MHz. Q
REG
is a regenerated version
of the input clock frequency.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
IDT5T940
DESCRIPTION:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the Q
OUT
is a multiplied
version of the input clock while Q
REG
is a regenerated version of the input clock.
When SELmode is mid, the Q
OUT
is a multiplied version of the input clock while
Q
REG
is Q
OUT
/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLLBW
1
PLLBW
0
Q
REG
PLL
DIV
N
Q
REG
CLKIN
CLKIN
INPUT
MUX
Q
OUT
DIV
M
Q
OUT
REFIN
REFIN
LOCK,
FREQ.
DETECTOR
CONTROL
LOGIC
PD
LOCK
SEL
MODE
CLK/
REF
0
CLK/
REF
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
OCTOBER 2008
DSC 6195/27

5T940-30NLI8 Related Products

5T940-30NLI8 5T940-10NLI 5T940-30NLI
Description Low Skew Clock Driver, PQCC28 PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC, VFQFPN-28 PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC, VFQFPN-28
Is it lead-free? Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code not_compliant not_compliant not_compliant
ECCN code EAR99 EAR99 EAR99
JESD-30 code S-PQCC-N28 S-PQCC-N28 S-PQCC-N28
JESD-609 code e0 e0 e0
Logic integrated circuit type LOW SKEW CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 1 1 1
Number of terminals 28 28 28
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QCCN HVQCCN HVQCCN
Encapsulate equivalent code LCC28,.24SQ,25 LCC28,.24SQ,25 LCC28,.24SQ,25
Package shape SQUARE SQUARE SQUARE
Package form CHIP CARRIER CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 225 240 240
power supply 2.5/3.3 V 2.5/3.3 V 2.5/3.3 V
Certification status Not Qualified Not Qualified Not Qualified
surface mount YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 0.635 mm 0.65 mm 0.65 mm
Terminal location QUAD QUAD QUAD
Maximum time at peak reflow temperature 30 20 20
Parts packaging code - QFN QFN
package instruction - HVQCCN, LCC28,.24SQ,25 PLASTIC, VFQFPN-28
Contacts - 28 28
Manufacturer packaging code - VFQFPN VFQFPN
series - 5T 5T
Input adjustment - DIFFERENTIAL MUX DIFFERENTIAL MUX
length - 6 mm 6 mm
Number of functions - 1 1
Actual output times - 2 2
Same Edge Skew-Max(tskwd) - 0.02 ns 0.02 ns
Maximum seat height - 1 mm 1 mm
Maximum supply voltage (Vsup) - 3.465 V 3.465 V
Minimum supply voltage (Vsup) - 2.375 V 2.375 V
Nominal supply voltage (Vsup) - 2.5 V 2.5 V
width - 6 mm 6 mm
minfmax - 666.52 MHz 666.52 MHz
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