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5962F9655601QCA

Description
AC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14, CERAMIC, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size240KB,10 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962F9655601QCA Overview

AC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

5962F9655601QCA Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
Counting directionRIGHT
seriesAC
JESD-30 codeR-CDIP-T14
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Number of digits8
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)21 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose300k Rad(Si) V
Trigger typePOSITIVE EDGE
width7.62 mm
Base Number Matches1
Standard Products
UT54ACS164/UT54ACTS164
8-Bit Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS164 - SMD 5962-96556
UT54ACTS164 - SMD 5962-96557
DESCRIPTION
PINOUTS
14-Pin DIP
Top View
A
B
Q
A
Q
B
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
14-Lead Flatpack
Top View
A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
The UT54ACS164 and the UT54ACTS164 are 8-bit shift reg-
isters which feature AND-gated serial inputs and an asynchro-
nous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met. Clock-
ing occurs on the low-to-high-level transition of the clock input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
A0
H
L
L
OUTPUTS
Q
B
L
Q
B0
Q
An
Q
An
Q
An
...
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
B
Q
A
Q
B
Q
C
Q
D
V
SS
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A
(1)
(2)
SRG8
R
C1/
&
1D
(3)
(4)
Q
H
L
Q
H0
Q
Gn
Q
Gn
Q
Gn
B
Q
A
Q
B
(5)
Q
(6)
C
Q
D
(10)
Q
(11)
E
Q
(12)
F
Q
(13)
G
Q
H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Notes:
1. Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
or Q
H
, respectively, before the indicated
steady-state input conditions were established.
2. Q
An
and Q
Gn
= the level of Q
A
or Q
G
before the most recent
transition of
the clock; indicates a one-bit shift.
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