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5962R0822801QYC

Description
Microprocessor, 32-Bit, 66MHz, CMOS, CBGA484, HERMETIC SEALED, CERAMIC PACKAGE-484
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size909KB,47 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962R0822801QYC Overview

Microprocessor, 32-Bit, 66MHz, CMOS, CBGA484, HERMETIC SEALED, CERAMIC PACKAGE-484

5962R0822801QYC Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionLGA, LGA484,22X22,50
Reach Compliance Codeunknown
Address bus width32
bit size32
boundary scanYES
maximum clock frequency66 MHz
External data bus width32
FormatFIXED POINT
Integrated cacheNO
JESD-30 codeS-CBGA-N484
JESD-609 codee4
length28.96 mm
low power modeYES
Number of terminals484
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeLGA
Encapsulate equivalent codeLGA484,22X22,50
Package shapeSQUARE
Package formGRID ARRAY
power supply2.5,3.3 V
Certification statusQualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height3.2 mm
speed66 MHz
Maximum slew rate1782 mA
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceGOLD OVER NICKEL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationBOTTOM
width28.96 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR
Base Number Matches1
REVISIONS
LTR
A
B
DESCRIPTION
Add case outline Y. Change memory skew timing , t9, in Table I. - PHN
Change the maximum values of Core supply voltage and I/O supply voltage in section
1.3. Change and add the tests for t
22
, t
23a
, t
23b
, t
24
in Table IA. Change Figure 13 and
add Figure 14 for timing waveforms and test circuits. Update boilerplate to current
MIL-PRF-38535 requirements. - PHN
DATE (
YR-MO-DA
)
10-01-06
13-02-19
APPROVED
Thomas M. Hess
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
B
35
B
15
B
36
B
16
B
37
B
17
B
38
B
18
REV
B
39
B
19
B
40
B
20
B
41
B
21
B
1
B
42
B
22
B
2
B
43
B
23
B
3
B
44
B
24
B
4
B
45
B
25
B
5
B
46
B
26
B
6
B
27
B
7
B
28
B
8
B
29
B
9
B
30
B
10
B
31
B
11
B
32
B
12
B
33
B
13
B
34
B
14
SHEET
PREPARED BY
PMIC N/A
Charles F. Saffle
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Charles F. Saffle
APPROVED BY
Thomas M. Hess
DRAWING APPROVAL DATE
09-05-28
REVISION LEVEL
SIZE
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, CMOS, RADIATION
HARDENED, 32-BIT FAULT-TOLERANT V8/LEON 3FT
PROCESSOR, MONOLITHIC SILICON
CAGE CODE
AMSC N/A
B
A
SHEET
1
67268
OF
46
5962-08228
DSCC FORM 2233
APR 97
5962-E271-13
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