5962R1020501QXC datasheet, PDF

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5962R1020501QXC: DescriptionStandard SRAM, 1MX39, 20ns, CMOS, QFP-132; Categorystorage storage; File Size188KB，24 Pages; ManufacturerCobham PLC

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5962R1020501QXC Overview

Standard SRAM, 1MX39, 20ns, CMOS, QFP-132

5962R1020501QXC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cobham PLC
package instruction	GQFP, TPAK132,1.8SQ,25
Reach Compliance Code	unknown
Maximum access time	20 ns
Other features	ALSO OPERATES AT 2.3 V TO 3.6 V SUPPLY
I/O type	COMMON
JESD-30 code	S-XQFP-G132
length	22.86 mm
memory density	40894464 bit
Memory IC Type	STANDARD SRAM
memory width	39
Number of functions	1
Number of terminals	132
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-55 °C
organize	1MX39
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	GQFP
Encapsulate equivalent code	TPAK132,1.8SQ,25
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
Parallel/Serial	PARALLEL
power supply	1.8,2.5/3.3 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	7.87 mm
Maximum standby current	0.047 A
Minimum standby current	1 V
Maximum slew rate	0.225 mA
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.9 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
width	22.86 mm
Base Number Matches	1

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Standard Products

UT8R1M39 40Megabit SRAM MCM

UT8R2M39 80Megabit SRAM MCM

UT8R4M39 160Megabit SRAM MCM

Preliminary Data Sheet

June 8, 2011

www.aeroflex.com/memories

FEATURES



20ns Read, 10ns Write maximum access times available



Functionally compatible with traditional 1M, 2M, or 4M x

39 SRAM devices



CMOS compatible input and output levels, three-state

bidirectional data bus

- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0V core



Available densities:

- UT8R1M39: 40, 894, 464 bits

- UT8R2M39: 81, 788, 928 bits

- UT8R4M39: 163, 577, 856 bits



Operational Environment:

- Total-dose: 100 krad(Si)

- SEL Immune: 111MeV-cm

/mg

- SEU error rate = 6.3x10

-7

errors/bit-day assuming

geosynchronous orbit, Adam’s 90% worst environment.



Packaging options:

- 132-lead side-brazed dual cavity ceramic quad flatpack



Standard Microelectronics Drawing:

- UT8R1M39: 5962-10205

- QML Q, Q+ and V compliant part

- UT8R2M39: 5962-10206

- QML Q, Q+ and V pending

- UT8R4M39: 5962-10207

- QML Q, Q+ and V pending

INTRODUCTION

The UT8R1M39, UT8R2M39, and UT8R4M39 are high

performance CMOS static RAM multichip modules (MCMs)

organized as two, four, or eight individual 524,288 words x 39

bits dice respectively. Easy memory expansion is provided by

active LOW chip enables (En), an active LOW output enable

(G), and three-state drivers. This device has a power-down

feature that reduces power consumption by more than 90% when

deselected.

Writing to the device is accomplished by driving one of the chip

enable (En) inputs LOW and the write enable (W) input LOW.

Data on the 39 I/O pins (DQ0 through DQ38) is then written into

the location specified on the address pins (A0 through A18).

Reading from the device is accomplished by driving one of the

chip enables (En) and output enable (G) LOW while driving

write enable (W) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

Note:

Only one En pin may be active at any time.

The 39 input/output pins (DQ0 through DQ38) are placed in a

high impedance state when the device is deselected (En HIGH),

the outputs are disabled (G HIGH), or during a write operation

(En LOW, W LOW).

Figure 1. Block Diagram

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