EEWORLDEEWORLDEEWORLD

Part Number

Search

531WC1095M00DG

Description
CMOS/TTL Output Clock Oscillator, 1095MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531WC1095M00DG Overview

CMOS/TTL Output Clock Oscillator, 1095MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531WC1095M00DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency1095 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
A problem that has troubled me for a long time. I hope to get help from the masters (VXWORKS PCI9054
This is my first time developing a PCI9054 driver under vxWorks, and I have encountered many problems. The card is correctly accessed using memory mapping under Windows, but I have not tested access u...
huangqi412 Real-time operating system RTOS
Pingtouge recommends adding a keyword input matching function when selecting tags for blog posts
When I was posting a blog, I could only select tags with the mouse, and the webpage would go blank when I typed keywords on the keyboard. I began to suspect that it was a browser problem, so I switche...
littleshrimp Domestic Chip Exchange
Some algorithmic problems of fpga divider
Friends who have been learning FPGA for a while, do you have better ideas for divider design? At present, my ideas are limited to [color=red]shift -> compare -> subtract[/color], and I hope friends wi...
xuhongming FPGA/CPLD
Does anyone have the program for the 89C2051 electronic clock?
Thank you, if anyone has this program, please give me some advice. If you found it on a website, please leave the URL. Thank you....
god 51mcu
Weak signal detection circuit analysis, ultrasonic detection
Please analyze this circuit. The signal path is as follows: Ultrasonic signal (very small amplitude, a few millivolts to tens of millivolts) enters from the probe -----> C22 isolates the DC component ...
gaoyang9992006 Analog electronics
Synchronous Dual-Port RAM Module Example
Synchronous dual-port RAM module, you can understand how it works by looking at the parameters, so I will not say more, you can directly copy it to your own project for use. // synthesis verilog_input...
eeleader FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2393  2574  87  2732  2748  49  52  2  56  47 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号