534BA000293BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 534BA000293BG

534BA000293BG: DescriptionLVDS Output Clock Oscillator, 131.25MHz Nom, ROHS COMPLIANT, SMD, 8 PIN; CategoryPassive components oscillator; File Size3MB，43 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

534BA000293BG Overview

LVDS Output Clock Oscillator, 131.25MHz Nom, ROHS COMPLIANT, SMD, 8 PIN

534BA000293BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	IT CAN ALSO OPERATE AT 125 MHZ, 105 MHZ AND 100 MHZ
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	534
Installation features	SURFACE MOUNT
Nominal operating frequency	131.25 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	177.8mm x 127.0mm x 41.91mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

Si534

U A D

R E Q U E N C Y

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

Four selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

FS[1]

GND

FS[0]

Description

The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si534

is available with any-rate output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is

required for each output frequency, the Si534 uses one fixed crystal to

provide a wide range of output frequencies. This IC based approach allows

the crystal resonator to provide exceptional frequency stability and reliability.

In addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low jitter clocks in noisy environments

typically found in communication systems. The Si534 IC-based XO is factory

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, and temperature stability. Specific

configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

CLK–

CLK+

(LVDS/LVPECL/CML)

FS[1]

GND

FS[0]

Functional Block Diagram

CLK– CLK+

CLK

FS[1]

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

FS[0]

(CMOS)

GND

Rev. 1.0 7/06

Si534

Recommended Resources

TDA1554Q power amplifier circuit diagram

Active double tuned filter circuit

Wrong phase and phase loss protection circuit

MC34018 hands-free calling circuit

Bidirectional trigger diode (DIAC)

555 variable delay lighting self-extinguishing circuit

TI CC2650 BoosterPack and TI CC2650 Launchpad Unboxing: I am very happy to receive the TI wireless kit so quickly. I placed the order last Friday and it arrived in two days. It is really fast. Let me show you the unboxing photos first.The TI CC2650 Booster...; qwerghf Microcontroller MCU

I want to make a three-phase PFC rectifier circuit but don't know how to do it. Please help me.: I know a little about the three-phase rectifier main circuit, but I don't know how to simulate it in simulink. My diagram always goes wrong when I simulate it in MATLAB. I don't know what's wrong. If ...; zem1234 Power technology

1602lcd display problem: I wrote the program myself, but the LCD does not display characters. Please give me some advice./************************************************************ * Company Name: * Creator: Kuang Wei Creat...; eeworldcom Embedded System

Design of wireless mobile charging power supply: I saw someone DIY a wireless mobile power bank on the forum. If you want to convert it into production, please contact Mr. Zhu at 13798801628. [[i] This post was last edited by court on 2013-9-15 08:4...; court Power technology

Address alignment trap problem occurs when ARM controls FPGA IP core: The control register uses the IP base address + offset method h2p_lw_ctl_addr=virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_LED_BASE + [color=#ff0000]0x00000001[/color]) & ( unsigned l...; LiFan123 FPGA/CPLD

Resonant soft switching technology and its application in inverter power supply: Resonant soft switching technology and its application in inverter power supply Abstract: In order to obtain higher performance indicators, higher efficiency, and higher power density, soft switching ...; zbz0529 Power technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components