550MF000127DG datasheet, PDF - EEWORLD Datasheet

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550MF000127DG: DescriptionLVPECL Output Clock Oscillator, ROHS COMPLIANT PACKAGE-6; CategoryPassive components oscillator; File Size326KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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550MF000127DG Overview

LVPECL Output Clock Oscillator, ROHS COMPLIANT PACKAGE-6

550MF000127DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT PACKAGE-6
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION; TRAY
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	100 ppm
frequency stability	50%
linearity	10%
Manufacturer's serial number	SI550
Installation features	SURFACE MOUNT
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Base Number Matches	1

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Si550

EVISION

O L TAG E

- C

ONTR OLLED

RYSTAL

S C I L L A T O R

(VCXO)

10 MH

Z TO

1.4 G H

Features

Available with any frequency from



10 to 945 MHz and select

frequencies to 1.4 GHz



3rd generation DSPLL

with

superior jitter performance (0.5 ps)



3x better temperature stability than



SAW-based oscillators



Excellent PSRR performance



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 10.

Applications



SONET/SDH

xDSL

10 GbE LAN/WAN



Low-jitter clock generation

Optical modules

Clock and data recovery

Pin Assignments:

See page 9.

(Top View)

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to

provide a low-jitter clock at high frequencies. The Si550 supports any

frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike

traditional VCXOs, where a different crystal is required for each output

frequency, the Si550 uses one fixed crystal to provide a wide range of output

frequencies. This IC-based approach allows the crystal resonator to provide

exceptional frequency stability and reliability. In addition, DSPLL clock

synthesis provides superior supply noise rejection, simplifying the task of

generating low-jitter clocks in noisy environments typically found in

communication systems. The Si550 IC-based VCXO is factory-configurable

for a wide variety of user specifications, including frequency, supply voltage,

output format, tuning slope, and temperature stability. Specific configurations

are factory programmed at time of shipment, thereby eliminating the long

lead times associated with custom oscillators.

CLK–

GND

CLK+

Functional Block Diagram

Fixed

Frequency

Any-Frequency

10 MHz–1.4 GHz

DSPLL

Clock Synthesis

CLK+

CLK–

ADC

GND

Rev. 1.1 4/13

Si550

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