530QC978M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530QC978M000DG

530QC978M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 978MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530QC978M000DG Overview

CMOS/TTL Output Clock Oscillator, 978MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530QC978M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	978 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

One of the circuits to prevent reverse polarity of DC power supply

Temperature measurement bridge circuit

Electrical schematic diagram of G607 circular sawing machine

AC single pole double throw switch circuit diagram

High definition! Electric bicycle circuit diagram in Gongli ZYS

Phase loss protection circuit for three-phase three-wire system

SDRAM delay parameter setting: I continue to study Teacher Quanhui's FPGA control SDRAM program. I have a question about how to set the delay parameters. The specific code is as follows: sdram_ctrl //SDRAM timing delay parameter pa...; siyu FPGA/CPLD

[My relationship with TI] + TI op amps support electronics competition: {:1_140:}Last time I talked with you about the reason why [color=#000][font=微软雅黑][size=4] [[/size][/font][/color][color=rgb(0, 0, 0)][font=微软雅黑][size=4][color=#FF0000]My relationship with TI[/color][/...; High哥 TI Technology Forum

Three special PCB routing techniques: right-angle routing, differential routing, and serpentine routing: [align=left][color=rgb(51, 51, 51)][font=-apple-system-font, BlinkMacSystemFont, "][size=17px]Layout is one of the most basic working skills for PCB design engineers. The quality of routing will direc...; ohahaha PCB Design

I received the Kindle e-book. I'll show it to you.: [i=s] This post was last edited by Brother Bath on 2014-10-15 12:38 [/i] Thanks to Jun Yixing for the forum, the picture above. The paper screen looks very comfortable~...; 洗澡哥 Embedded System

msp430 br instruction usage: asm("br #0x8066"); means jumping to the address 0x8066 to execute asm("br &0x8066"); is equivalent to m("br 0x8066"); means jumping to the address in the storage space 0x8066 to execute In the memory ...; Jacktang Microcontroller MCU

EEWORLD University - 3 ways to quickly adapt to changing Ethernet protocols: 3 ways to quickly adapt to changing Ethernet protocols : https://training.eeworld.com.cn/course/2143Can your designs quickly adapt to changing Ethernet protocols? Can you meet increasing performance r...; chenyy FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components