531HC562M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531HC562M000DG

531HC562M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 562MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531HC562M000DG Overview

CMOS/TTL Output Clock Oscillator, 562MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531HC562M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	562 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

TX5/RX5 circuit-b

50V suspended regulated power supply diagram

Lilong brand RTP-18 tea set disinfection cabinet circuit diagram

Charger circuit diagram using M51849L

555 practical digital level probe circuit

Circuit diagram of 12V valve-controlled sealed lead-acid battery dual-level float charger UC3960

A review on harmonic issues in power electronic devices: A review on harmonic issues in power electronic devices Abstract: With the development of power electronics technology, the harm of harmonics has become more and more serious, and the harmonic control...; zbz0529 Embedded System

TI DaVinci Technology: What is Da Vinci Technology?TI's official website has a detailed introduction to Da Vinci technology. Da Vinci technology is not only a DSP+ARM dual-core architecture SOC chip, it also includes a comp...; Jacktang DSP and ARM Processors

Ask a question about the clock: I am a 430 beginner, and I would like to ask a question about the clock. How are the several clocks in msp430 used? Can the several clocks be used for any module, or can some modules only use specific...; 把握今天守望 Microcontroller MCU

【Learning experience】DLP micro-projection technology: DLP is the abbreviation of Dightial Light Processing, which is digital optical processing. Using DLP technology, optical images can be projected onto a large screen after digital processing. DMD is th...; lonerzf TI Technology Forum

About F2808 SPI edge capture: When debugging the F2808 SPI routine, I have a question to ask. According to the routine, the high-speed algorithm uses the timeout event for calculation, so the time is fixed and the position informa...; wangly Microcontroller MCU

Award-winning review: Mir Allwinner automotive-grade CPU development board MYC-YT507: Model: MYD-YT507-8E1D-150-I (industrial grade), value 650 yuan Quantity: 3 sets The MYC-YT507 core board is based on the Allwinner automotive-grade T507 processor, which integrates a quad-core Cortex-...; EEWORLD社区 Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components