EEWORLDEEWORLDEEWORLD

Part Number

Search

531RB1087M00DGR

Description
LVPECL Output Clock Oscillator, 1087MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531RB1087M00DGR Overview

LVPECL Output Clock Oscillator, 1087MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531RB1087M00DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency1087 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
msp430x15x 430x16x 430x161x datasheet
msp430x15x 430x16x 430x161x datasheet [[i] This post was last edited by guanglin on 2011-8-2 11:06[/i]]...
guanglin Microcontroller MCU
I am a novice and want to learn how to port ucgui under stm32. How should I start?
I am a novice who wants to learn how to port ucgui under stm32. I have found some information, which are basically ucgui manuals. I don't know how to start. I want to find a video to learn, but I can'...
1989despair Real-time operating system RTOS
Question about MSP430F6736 UCS!
I made a board with 6736. When initializing UCS, the initialization code is as follows: PJDIR |= BIT0 | BIT1 | BIT3; // ACLK, MCLK, SMCLK set out to pins PJSEL |= BIT0 | BIT1 | BIT3; // PJ.0,1,3 for d...
qdavid64 Microcontroller MCU
FPGA SPI Communication Discussion
I am doing a small experiment of FPGA and MCU communication, and I have encountered a problem. Please guide me. The current situation is that the MCU runs first, and then the FPGA starts to run, and t...
cclcxy FPGA/CPLD
C2000 Power-on Boot Mode Analysis
When using C2000, engineers often say that the chip simulation can run, but the stand-alone run cannot run; or when debugging, reset the chip > run, and find that the program cannot run. The main reas...
Jacktang Microcontroller MCU
[Help] Please help me look at this circuit. + voltage has no output, - voltage is normal
After power on, Q9 G pole has 4V voltage (normally there is no voltage), D pole has 0.7V (normally 5V), I don't know where the fault is, please help me analyze it...
卟呤、卟呤 Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 319  962  1660  1835  2204  7  20  34  37  45 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号