530QB1075M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530QB1075M00DG

530QB1075M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1075MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530QB1075M00DG Overview

CMOS/TTL Output Clock Oscillator, 1075MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530QB1075M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1075 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Blocking monitoring circuit

Music TM80200 series music integrated circuit

Switching regulator circuit diagram with one additional switch tube

Fault prevention method b when two power supplies are connected in series

Tape head and tail detector circuit

The structure of D-type IPM and the equivalent circuit of IGBT

How to process and display the data received by UART from HS0038B: How to process the data (character hexadecimal - infrared temperature transmission) received by UART from HS0038B and send it to the digital tube (via SPI)? The main problem to be solved is how to pro...; 乁year Microcontroller MCU

Learn to use STM8 day by day: On the first day, I figured out download an debug of IAR + STLINK.What was frustrating was that the STLINK on the STM three-in-one development board I bought could not connect to the machine, so I too...; mati1111 stm32/stm8

Teach you how to program--Programmer Programming Art: （Original post from [url=http://blog.csdn.net/v_july_v/article/details/17303459#comments]http://blog.csdn.net/v_july_v/article/details/17303459#comments[/url]） [p=26, null, left][color=#333333][font=A...; tiankai001 Download Centre

How to use EBI in AT91RM9200 ARM to connect to Nor Flash in Page Mode: The controllers that can be used to mount Flash in EBI seem to include: Burst Flash Controller, NAND Flash/SmartMedia Logic, and CompactFlash Logic (datasheet attached)I want to install a Page Mode No...; zhangqh08 ARM Technology

FPGA Simple Design Method for Efficient Design: Minimalistic design method for efficient design In the previous section, we described Ming Deyang's general design method. In the process of explaining the case, we drew a lot of waveform diagrams. So...; mdy-吴伟杰 FPGA/CPLD

Furnace temperature detection: ...; 王子 MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components