531DA1047M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531DA1047M00DGR

531DA1047M00DGR: DescriptionCMOS/TTL Output Clock Oscillator, 1047MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531DA1047M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1047MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531DA1047M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1047 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Sound and light controlled timing power-saving switch circuit

STK4161 II power amplifier circuit diagram

Low frequency amplifier circuit for radio receiver

L200 constitutes the soft start circuit diagram in the power supply

IBM PC and MCS-51 multi-machine communication

IGBT drive protection circuit

Transfer 4 network cameras, with PTZ, only 4* yuan: 4 cameras for sale at a bargain price, 49.8 yuan each, brand new with pan/tilt head, can be used with just an internet cable and a 12V power supply, you can use this camera to see what's going on at h...; rogerangel Buy&Sell

Open source ISP-VB6 source code, only supports AT89S51/AT89S52: ISP-VB6.0 source code for AT89S51 and AT89S52. There is no confidentiality button, please avoid it if you are an enterprise user. There is no erase button either, please create an empty .HEX file to e...; xu__changhua 51mcu

How to simulate the total interruption of STM8?: When I use stm8s105, I want to simulate the status of the total interruption, but I only know the C language for opening/closing:enableInterrupts();disableInterrupts();the corresponding assembly is RI...; tomato20886 stm32/stm8

C6678 Multi-core DSP Software Development Difficulties and Solutions: C6678 multi-core DSP, more complicated to useComplex octa-core DSP (CorePAC core manual is 250 pages!) Complex DSP peripherals (RapidIO, Ethernet, CDMA, thousands of pages of hardware manuals!) Dizzy ...; Jacktang Microcontroller MCU

【Foreign investment】【Electronic engineer】【Annual salary 100,000-180,000 yuan】: A Fortune 500 company is recruiting electronic engineers. Job responsibilities: Responsible for the design and development of LED lighting electronic circuits: Improvement and development of driver pr...; xuanyuandingruo Recruitment

Haha, I received two books from the forum this morning.: Haha, I received two books from the forum this morning. I was excited and touched when I got them. Thank you forum! ~Study hard in the future and don’t waste resources! ~...; wanghongyang FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components