530MB844M000BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530MB844M000BG

530MB844M000BG: DescriptionLVPECL Output Clock Oscillator, 844MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530MB844M000BG Overview

LVPECL Output Clock Oscillator, 844MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MB844M000BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	844 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

What are the three changes in power distribution structure?

One control two constant pressure water supply frequency conversion speed control circuit b

Simple mobile flash circuit

thyristor relaxation flasher

High level water storage container water level control circuit

875p computer motherboard circuit diagram_044

Error when using STM32 DMA: The initialization procedure is as follows: DMA_DeInit(DMA1_Channel1);//Reset DMA channel 1 DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address; //Define DMA channel peripheral base address = A...; Mrye stm32/stm8

What does void (*oper(ChainBinTree *p ))) mean?: I've been studying binary tree algorithms recently, which involves the implementation of traversal. Here's the definition of a binary tree traversal function in the book: void BinTree_LDR(ChainBinTree...; HALO--117 Programming Basics

Share DDR2 control Verilog HDL program code: [size=4]The source program is as follows:[/size] [size=4]//---------------------------------------------------------------------------[/size] [size=4]//-- File name: Project_Ddr2.v[/size] [size=4]//--...; fish001 DSP and ARM Processors

Good stuff sharing, Cadence SPB15.7 video tutorial 1-7 (Dr. Yu version): You can watch it online or download it. The file is too large to upload. Here is the address, you can download it yourself. [url=http://www.sig007.com/videoclass/107.html]http://www.sig007.com/videocl...; cheeta PCB Design

Or EEPROM? How to use software to determine the size of EEPROM?: RT, I don't know if I can judge the size of an EEPROM by reading and writing abnormalities outside the address. For example, if an 8K EEPROM is written to an area outside the 8K area, if an abnormalit...; fjw10245 Embedded System

After waking up, the system freezes and no interrupt signal is found, but interrupts are continuously generated? ?: My situation is this: After waking up 2450 WinCE5.0, the machine freezes: except for a static image on the display, the system does not respond to other peripherals. Through the printed information, I...; Kane204 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components