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QL6250-E-6PQ208I

Description
FPGA, 960 CLBS, 248160 GATES, PQFP208, PLASTIC, QFP-208
CategoryProgrammable logic devices    Programmable logic   
File Size337KB,37 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Download Datasheet Parametric View All

QL6250-E-6PQ208I Overview

FPGA, 960 CLBS, 248160 GATES, PQFP208, PLASTIC, QFP-208

QL6250-E-6PQ208I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFP
package instructionFQFP,
Contacts208
Reach Compliance Codecompliant
Combined latency of CLB-Max0.3238 ns
JESD-30 codeS-PQFP-G208
length28 mm
Configurable number of logic blocks960
Equivalent number of gates248160
Number of terminals208
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize960 CLBS, 248160 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.13 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
Base Number Matches1
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0.18 µm six layer metal CMOS Process
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1.8/2.5/3.3 V Drive Capable I/O
‡
960 Logic Cells
‡
248,160 Max System Gates
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Up to 250 I/O Pins
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Nine Global Clock Networks:
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One Dedicated
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Eight Programmable
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20 Quad-Net Networks—five per Quadrant
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16 I/O Controls—two per I/O Bank
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Four phase locked loops
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Twenty 2,304-bit Dual Port High
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10 ECUs provide integrated Multiply, Add, and
Accumulate Functions.
Performance SRAM Blocks
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46,100 RAM bits
‡
RAM/ROM/FIFO Wizard for Automatic
Configuration
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Configurable and Cascadable
PLL
Embedded RAM Blocks
10 Embeded Computational Units
PLL
3URJUDPPDEOH ,2
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High performance Enhanced I/O (EIO)—
less than 3 ns Tco
‡
Programmable Slew Rate Control
‡
Programmable I/O Standards:
‡
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
‡
Eight Independent I/O Banks
‡
Three Register Configurations: Input,
Output, and Output Enable
Fabric
PLL
Embedded RAM Blocks
PLL
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