QL6250-E-6PS484C datasheet, PDF

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QL6250-E-6PS484C: DescriptionFPGA, 960 CLBS, 248160 GATES, PBGA484, 1 MM PITCH, PLASTIC, BGA-484; CategoryProgrammable logic devices Programmable logic; File Size337KB，37 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL6250-E-6PS484C Overview

FPGA, 960 CLBS, 248160 GATES, PBGA484, 1 MM PITCH, PLASTIC, BGA-484

QL6250-E-6PS484C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA,
Contacts	484
Reach Compliance Code	compliant
Combined latency of CLB-Max	0.3161 ns
JESD-30 code	S-PBGA-B484
length	23 mm
Configurable number of logic blocks	960
Equivalent number of gates	248160
Number of terminals	484
Maximum operating temperature	70 °C
Minimum operating temperature
organize	960 CLBS, 248160 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.14 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	23 mm
Base Number Matches	1

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0.18 µm six layer metal CMOS Process

1.8/2.5/3.3 V Drive Capable I/O

960 Logic Cells

248,160 Max System Gates

Up to 250 I/O Pins

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Nine Global Clock Networks:

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Eight Programmable

20 Quad-Net Networks—five per Quadrant

16 I/O Controls—two per I/O Bank

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Performance SRAM Blocks

46,100 RAM bits

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Embedded RAM Blocks

10 Embeded Computational Units

PLL

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High performance Enhanced I/O (EIO)—

less than 3 ns Tco

Programmable Slew Rate Control

Programmable I/O Standards:

LVTTL, LVCMOS, PCI, GTL+, SSTL2,

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Eight Independent I/O Banks

Three Register Configurations: Input,

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