QL6250E-6PS484I datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> QL6250E-6PS484I

QL6250E-6PS484I: DescriptionField Programmable Gate Array, 960 CLBs, 248160 Gates, 960-Cell, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484; CategoryProgrammable logic devices Programmable logic; File Size850KB，64 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

Download Datasheet Parametric View All

QL6250E-6PS484I Overview

Field Programmable Gate Array, 960 CLBs, 248160 Gates, 960-Cell, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484

QL6250E-6PS484I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA484,22X22,40
Contacts	484
Reach Compliance Code	compliant
Combined latency of CLB-Max	1.3916 ns
JESD-30 code	S-PBGA-B484
length	23 mm
Humidity sensitivity level	3
Configurable number of logic blocks	960
Equivalent number of gates	248160
Number of entries	250
Number of logical units	960
Output times	250
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	960 CLBS, 248160 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA484,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8/3.3,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.34 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	23 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Eclipse-E Family Data Sheet

••••••

FPGA Combining Performance, Density, and Embedded RAM

Device Highlights

Flexible Programmable Logic

• 0.18 µm six layer metal CMOS process

• 1.8/2.5/3.3 V drive capable I/O

• Up to 1536 logic cells

• Up to 4,002 flip-flops

• Up to 310 I/O pins

• Up to 335 user-available pins

• Up to 320,460 maximum system gates

Advanced Clock Network

• Nine global clock networks:

One dedicated

Eight programmable

• 20 quad-net networks—five per quadrant

• 16 I/O controls—two per I/O bank

• Four phase locked loops

Embedded Computational Units

ECUs provide integrated multiply, add, and

accumulate functions.

Embedded Dual Port SRAM

• Up to twenty-four 2,304-bit dual port high

performance SRAM blocks

• Up to 55,296 RAM bits

• RAM/ROM/FIFO wizard for automatic

configuration

• Configurable and cascadable

Security Features

The QuickLogic products come with secure

ViaLink® technology that protects intellectual

property from design theft and reverse engineering.

No external configuration memory needed;

instant-on at power-up.

Figure 1: Eclipse-E Block Diagram

Programmable I/O

• High performance I/O cell

• Programmable slew rate control

• Programmable I/O standards:

LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,

SSTL2, and SSTL3

Eight independent I/O banks

Three register configurations: Input, Output,

and Output Enable

PLL

Embedded RAM Blocks

Embeded Computational Units

PLL

Fabric

PLL

Embedded RAM Blocks

PLL

www.quicklogic.com

•

Eclipse-E Family Data Sheet Rev. A

RAM Modules

The Eclipse-E family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and

FIFO functions. Each module is user-configurable into four different block organizations and can be cascaded

horizontally to increase their effective width, or vertically to increase their effective depth as shown in

Figure 4.

Figure 3: 2,304-bit RAM Module

MODE[1:0]

WA[9:0]

WD[17:0]

WCLK

ASYNCRD

RA[9:0]

RD[17:0]

RCLK

Using the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are

also easily cascadable to increase their effective width and/or depth (see

Figure 4

)

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 256 words. In this case address signals higher

than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

•

www.quicklogic.com

•

Recommended Resources

A RKC XTE-7000 temperature controller circuit diagram

Electric sewing machine circuit

Low frequency voltage controlled oscillator circuit

Thermocouple Temperature Transmitter Circuit

Anti-interference measurement amplifier circuit

Bootstrap staircase wave circuit

Haha, the forum is back! That's fast! Thumbs up!: I was working on the questions! Suddenly! Then! The engineers at EEWORLD are still very capable! Thank you for your hard work!!...; wuyanyanke Microcontroller MCU

[2022 Digi-Key Innovation Design Competition] 3. Experience of using the official case of ESP32-S2-Kaluga-1: The Kaluga board has its own official case library. This article records the usage of the library. 1. Obtaining the case library The "esp-dev-kits" repository on the Espressif official site on GitHub ...; sonicfirr DigiKey Technology Zone

About borrowing money: Have you ever encountered someone who borrowed money but didn't pay it back? The amount of money borrowed was not large, only a few thousand yuan. If they don't pay it back, what are some effective wa...; UUC Talking

How to achieve software adjustable backlight brightness with 430F2274 MCU driving 12864 LCD: [size=4]How to achieve software-adjustable backlight brightness with 430F2274 MCU driving 12864 LCD instead of using variable resistor?[/size]...; nwx8899 Microcontroller MCU

C8051F340 Question about USBXpress (USBXpress pops up after downloading, why): I used C8051F340 to design, and used USB to communicate with PC. It was working fine before, but I don't know if it was because of reinstalling the system or something else, but now there is the follo...; lbj412 Embedded System

FFT Analysis of Vibration Information: [i=s]This post was last edited by lcdi on 2020-5-3 20:49[/i]From the perspective of signal processing, since the amplitude fluctuation is large and difficult to stabilize, this factor will be consider...; lcdi ST MEMS Sensor Creative Design Competition

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components