XC18V02PC44C datasheet, PDF - EEWORLD Datasheet

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XC18V02PC44C: Description256K X 8 CONFIGURATION MEMORY, 20 ns, PQCC44; Categorystorage storage; File Size279KB，24 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC18V02PC44C Overview

256K X 8 CONFIGURATION MEMORY, 20 ns, PQCC44

XC18V02PC44C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	LCC
package instruction	LCC-44
Contacts	44
Reach Compliance Code	_compli
ECCN code	EAR99
Factory Lead Time	12 weeks
Maximum access time	20 ns
Maximum clock frequency (fCLK)	20 MHz
Data retention time - minimum	20
Durability	20000 Write/Erase Cycles
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
memory density	2097152 bi
Memory IC Type	CONFIGURATION MEMORY
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL/SERIAL
Peak Reflow Temperature (Celsius)	225
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.01 A
Maximum slew rate	0.025 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	16.5862 mm

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XC18V00 Series In-System-Programmable

Configuration PROMs

Product Specification

DS026 (v5.2) January 11, 2008

Features

•

In-System Programmable 3.3V PROMs for

Configuration of Xilinx FPGAs

♦

•

Low-Power Advanced CMOS FLASH Process

Dual Configuration Modes

♦

Endurance of 20,000 Program/Erase Cycles

Program/Erase Over Full Industrial Voltage and

Temperature Range (–40

C to +85

•

Serial Slow/Fast Configuration (up to 33 MHz)

Parallel (up to 264 Mb/s at 33 MHz)

•

IEEE Std 1149.1 Boundary-Scan (JTAG) Support

JTAG Command Initiation of Standard FPGA

Configuration

Simple Interface to the FPGA

Cascadable for Storing Longer or Multiple Bitstreams

5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals

3.3V or 2.5V Output Capability

Design Support Using the Xilinx ISE™ Foundation™

Software Packages

Available in PC20, SO20, PC44, and VQ44 Packages

Lead-Free (Pb-Free) Packaging

Description

Xilinx introduces the XC18V00 series of in-system

programmable configuration PROMs (Figure

1).

Devices in

this 3.3V family include a 4-megabit, a 2-megabit, a

1-megabit, and a 512-kilobit PROM that provide an easy-to-

use, cost-effective method for reprogramming and storing

Xilinx FPGA configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after CE and OE are enabled, data is available on the

PROM DATA (D0) pin that is connected to the FPGA DIN

pin. New data is available a short access time after each

rising clock edge. The FPGA generates the appropriate

number of clock pulses to complete the configuration. When

the FPGA is in Slave Serial mode, the PROM and the FPGA

are clocked by an external clock.

X-Ref Target - Figure 1

When the FPGA is in Master SelectMAP mode, the FPGA

generates a configuration clock that drives the PROM. When

the FPGA is in Slave Parallel or Slave SelectMAP mode, an

external oscillator generates the configuration clock that

drives the PROM and the FPGA. After CE and OE are

enabled, data is available on the PROM’s DATA (D0-D7)

pins. New data is available a short access time after each

rising clock edge. The data is clocked into the FPGA on the

following rising edge of the CCLK. A free-running oscillator

can be used in the Slave Parallel or Slave SelecMAP modes.

Multiple devices can be cascaded by using the CEO output

to drive the CE input of the following device. The clock

inputs and the DATA outputs of all PROMs in this chain are

interconnected. All devices are compatible and can be

cascaded with other members of the family or with the

XC17V00 one-time programmable serial PROM family.

OE/RESET

CLK

TCK

TMS

TDI

TDO

Control

and

JTAG

Interface

Data

CEO

Memory

Address

Data

Serial

Parallel

Interface

D0 DATA

Serial or Parallel Mode

D[1:7]

Parallel Interface

DS026_01_040204

Figure 1:

XC18V00 Series Block Diagram

trademarks are the property of their respective owners.

DS026 (v5.2) January 11, 2008

Product Specification

www.xilinx.com

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