GS8180Q36D-133T datasheet, PDF

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GS8180Q36D-133T: DescriptionStandard SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size1MB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8180Q36D-133T Overview

Standard SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

GS8180Q36D-133T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm
Base Number Matches	1

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GS8180Q18/36D-200/167/133/100

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

• RoHS-compliant 165-bump BGA package available

18Mb Burst of 2

SigmaQuad SRAM

200 MHz–100 MHz

1.8 V V

1.8 V or 1.5 V I/O

various combinations of address bursting, output data

registering, and write cueing. Along with the Common I/O

family of SigmaRAMs, the SigmaQuad family of SRAMs

allows a user to implement the interface protocol best suited to

the task at hand.

Clocking and Addressing Schemes

A Burst of 2 SigmaQuad SRAM is a synchronous device. It

employs two input register clock inputs, K and K. K and K are

independent single-ended clock inputs, not differential inputs

to a single differential clock input buffer. The device also

allows the user to manipulate the output register clock inputs

quasi independently with the C and C clock inputs. C and C are

also independent single-ended clock inputs, not differential

inputs. If the C clocks are tied high, the K clocks are routed

internally to fire the output registers instead.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 1M x 18 has a 512K

addressable index).

SigmaRAM™ Family Overview

GS8180Q18 are built in compliance with the SigmaQuad

SRAM pinout standard for Separate I/O synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs. These are the first in

a family of wide, very low voltage HSTL I/O SRAMs designed

to operate at the speeds needed to implement economical high

performance networking systems.

SigmaQuad SRAMs are offered in a number of configurations.

Some emulate and enhance other synchronous separate I/O

SRAMs. A higher performance SDR (Single Data Rate) Burst

of 2 version is also offered. The logical differences between

the protocols employed by these RAMs hinge mainly on

Parameter Synopsis*

-167

6.0 ns

2.5 ns

-133

7.5 ns

3.0 ns

-100

10.0 ns

3.0 ns

-200

tKHKH

tKHQV

5.0 ns

2.3 ns

Rev: 2.06 10/2006

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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