To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
2002.10.18
Ver. 3.0
MITSUBISHI LSIs
M5M5Y816WG (-55HI), -70HI, -85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
The M5M5Y816 is a f amily of low v oltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.18µm CMOS technology .
The M5M5Y816 is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5Y816WG is packaged in a f -BGA (f ine pitch BGA),
with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It giv es the best solution f or
a compaction
of m ounting area as well as f lexibility of wiring pattern of printed
circuit boards.
Version,
Operating
temperature
Part name
-
-
-
-
-
-
-
-
-
-
-
FEATURES
Single 1.65~2.3V power supply
Small stand-by c urrent: 0.5µA (2.0V, ty p.)
No clocks, No ref resh
Data retention supply v oltage =1.3V
All inputs and outputs are TTL compatible.
Easy m emory expansion by S1#, S2, BC1# and BC2#
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.18µm CMOS
Package: 48ball 7.5mm x 8.5mm f -BGA
Power
Supply
Access time
max.
55ns
70ns
85ns
Activ e
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C (2.3V, max)
Stand-by c urrent (
µA
)
Ratings (max.)
* Ty pical
30mA
(10MHz)
5mA
(1MHz)
(M5M5Y 816WG -55HI) 1.65 ~ 2.3V
I-version
-40 ~ +85°C
M5M5Y816WG -70HI 1.65 ~ 2.3V
M5M5Y816WG -85HI 1.65 ~ 2.3V
0.5
1
2
4
15
30
* Typical parameter indicates the value for the center
of distribution at 2.0V, and not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1
A
B
C
D
E
F
G
H
BC1#
2
OE
3
A0
4
A1
5
A2
6
S2
Pin
DQ16
BC2#
A3
A4
S1#
DQ1
Function
Address input
A0 ~ A18
DQ14
DQ15
A5
A6
DQ2
DQ3
GND
DQ13
A17
NC or
GND
A7
DQ4
VCC
DQ1 ~ DQ16 Data input / output
S1#
Chip select input 1
S2
Chip select input 2
W#
OE
BC1#
BC2#
Vcc
GND
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
Ground supply
VCC
DQ12
A16
DQ5
GND
DQ11
DQ10
A14
A15
DQ7
DQ6
DQ9
N.C.
A12
A13
W#
DQ8
A18
A8
A9
A10
A11
N.C.
Outline:
48F7Q
NC: No Connection
*Don't connect E3 ball to v oltage lev el more than 0V
1
2002.10.18
Ver. 3.0
MITSUBISHI LSIs
M5M5Y816WG (-55HI), -70HI, -85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5Y 816WG is organized as 524288-words by
16-bit. These dev ices operate on a single +1.65~2.3V
power supply , and are directly TTL compatible to both
input and output. Its f ully static circuit needs no clocks
and no ref resh, and makes it usef ul.
The operation mode are determined by a combination
of the dev ice control inputs BC1# , BC2# , S1#, S2 ,
W# and OE#. Each mode is summarized in the f unction
table.
A write operation is executed whenev er the low lev el
W ov erlaps with the low lev el BC1# and/or BC2# and
the low lev el S1# and the high lev el S2. The
address(A0~A18) must be set up bef ore the write cy c le
and must be stable during the entire cy cle.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2#
and S1# and S2 are in an activ e state(S1#=L,S2=H).
When setting BC1# at the high lev el and other pins
are in an activ e stage , upper-by te are in a selectable
mode in which both reading and writing are enabled, and
lower-by te are in a non-selectable mode. And when
setting BC2# at a high lev el and other pins are in an
activ e stage, lower-by te are in a selectable mode and
upper-by te are in a non-selectable mode.
When setting BC1# and BC2# at a high lev el or S1# at a
high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by BC1#, BC2# and S1#, S2.
The power supply current is reduced as low as 0.5µA(25°C,
ty pical), and the memory data can be held at +1.3V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1# S2 BC1#BC2# W# OE#
Mode
Non selection
Non selection
Non selection
Non selection
DQ1~8
DQ9~16
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
H
X
H
H
H
H
H
H
H
H
H
X
X
X
H
L
L
L
H
H
H
L
L
L
X
X
X
H
H
H
H
L
L
L
L
L
L
X
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
X
L
H
X
L
H
X
L
H
Write
Read
Write
Read
Write
Read
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
Icc
Standby
Standby
Standby
Standby
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
BLOCK DIAGRAM
A
0
A
1
note1: "H" and "L" in this table mean V
IH
and V
IL,
respectiv ely .
note2: "X" in this table should be "H" or "L".
DQ
1
MEMORY ARRAY
524288 WORDS
x 16 BITS
DQ
8
-
A
16
A
18
S1#
S2
BC1#
CLOCK
GENERAT OR
DQ
9
DQ
16
BC2#
Vcc
W#
GND
OE#
2
2002.10.18
Ver. 3.0
MITSUBISHI LSIs
M5M5Y816WG (-55HI), -70HI, -85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Sy m bol
Parameter
Supply v oltage
Input v oltage
Output v oltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
I-v ersion
Ratings
Units
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.5
*
~ +2.7
-0.2
*
~ Vcc + 0.2 (max. 2.7V)
0 ~ Vcc
700
- 40 ~ +85
- 65 ~ +150
V
mW
°C
°C
* -0.7V in case of AC (Pulse width < 30ns)
=
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=1.65~ 2.3V, unless otherwise noted)
Conditions
Limits
Min
0.7xVcc
Ty p
Max
Vcc+0.2
Units
Parameter
High-lev el input v oltage
Low-lev el input v oltage
High-level output voltage
V
IH
V
IL
V
OH
V
OL
I
I
I
O
Low-lev el output v oltage
Input leakage current
Output leakage current
( AC,MOS lev el )
I
OH
= -0.1mA
I
OL
=0.1mA
V
I
=0
~
Vcc
BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc
BC1# and BC2# 0.2V, S1# 0.2V, S2
>
other inputs < 0.2V or = Vcc-0.2V
=
Output - open (duty 100%)
Vcc-0.2V
-0.2 *
1.3
0.4
0.2
±1
±1
30
5
30
5
2
4
15
30
0.5
V
µA
Icc
1 Activ e supply current
f = 10MHz
f = 1MHz
f = 10MHz
f = 1MHz
~ +25°C
~ +40°C
~ +70°C
~ +85°C
Activ e supply current
Icc
2
( AC,TTL lev el )
BC1# and BC2#=V
IL
, S1#=V
IL
,S2=V
IH
other pins =V
IH or
V
IL
Output - open (duty 100%)
>
(1)
S1# = Vcc - 0.2V,
> Vcc - 0.2V,
S2 =
other inputs = 0 ~ Vcc
(2)
S2 < 0.2V,
=
other inputs = 0 ~ Vcc
>
(3)
BC1# and BC2# = Vcc - 0.2V
>
S1 < 0.2V, S2 = Vcc - 0.2V
=
other inputs = 0 ~ Vcc
-
-
-
-
-
-
-
-
-
20
1.5
20
1.5
0.5
1
-
-
-
mA
Icc
3 Stand by s upply current
( AC,MOS lev el )
µA
Icc
4 Stand by s upply current
( AC,TTL lev el )
BC1# and BC2#=V
IH
or S1#=V
IH
or S2=V
IL
Other inputs= 0 ~ Vcc
mA
* -0.7V in case of AC (Pulse width < 30ns)
=
Note 3: Direction for current flowing into IC is indicated as positive (no mark)
Note 4: Typical parameter indicates the value for the center of distribution at 2.0V, and not 100% tested.
CAPACITANCE
Sy m bol
Parameter
Input capacitance
Output capacitance
Conditions
(Vcc=1.65 ~ 2.3V, unless otherwise noted)
Limits
Ty p
Units
Min
V
I
=GND, V
I
=25mVrms, f =1MHz
V
O
=
GND,V
O
=25mVrms, f =1MHz
Max
C
I
C
O
10
10
pF
3
2002.10.18
Ver. 3.0
MITSUBISHI LSIs
M5M5Y816WG (-55HI), -70HI, -85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
(Vcc=1.65 ~ 2.3V, unless otherwise noted)
1.65~2.3V
Input pulse
V
IH
=0.7 x Vcc+0.2V, V
IL
=0.2V
Input rise time and f all time
5ns
Ref erence lev el
Output loads
DQ
CL
1TTL
V
OH
=V
OL
=0.9V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Limits
Including scope and
jig capacitance
(2) READ CYCLE
Sy m bol
t
CR
t
a
(A)
t
a
(S1)
t
a
(S2)
t
a
(BC1)
t
a
(BC2)
t
a
(OE)
t
dis
(S1)
t
dis
(S2)
t
dis
(BC1)
t
dis
(BC2)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
t
en
(BC1)
t
en
(BC2)
t
en
(OE)
t
V
(A)
Parameter
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af ter S1# high
Output disable time af ter S2 low
Output disable time af ter BC1# high
Output disable time af ter BC2# high
Output disable time af ter OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time af ter address
Fig.1 Output load
(55HI)
Min
55
Max
55
55
55
55
55
30
20
20
20
20
20
5
5
5
5
5
5
70HI
Min
70
Max
70
70
70
70
70
35
25
25
25
25
25
10
10
5
5
5
10
Limits
85HI
Min
85
Max
85
85
85
85
85
45
30
30
30
30
30
10
10
5
5
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Sy m bol
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
(55HI)
Min
55
45
0
50
50
50
50
50
25
0
0
Max
70HI
Min
70
55
0
65
65
65
65
65
30
0
0
Max
85HI
Min
85
60
0
70
70
70
70
70
35
0
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
su
(S1)
t
su
(S2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
20
20
5
5
5
5
25
25
5
5
30
30
4
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