modulator designed specifically for digital flat panel
applications.
The
P2040A
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P2040A allows significant system
cost savings by reducing the number of circuit board
layers ferrite beads,
regulations.
The P2040A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The P2040A modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal
graphic
accelerator
produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called
‘spread spectrum clock generation’.
shielding and other passive
components that are traditionally required to pass EMI
components and board space.
Six selectable high spread ranges up to ± 2%.
Two selectable modulation rates.
SSON# control pin for spread spectrum enable
and disable options.
Low cycle-to-cycle jitter.
Wide operating range.
Low power CMOS design.
Supports
most
mobile
specifications.
Products available for automotive temperature
range.
•
(Refer
Spread
Spectrum
Range
Selection Tables)
Available in 8-pin SOIC and TSSOP Packages.
Applications
The P2040A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
VDD
Product Description
The P2040A is a versatile spread spectrum frequency
Block Diagram
SR0 SR1 MRA SSON#
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.3
Pin Configuration
CLKIN
MRA
SR1
VSS
1
2
8
7
P2040A
VDD
SR0
ModOUT
SSON#
P2040A
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip (3.3V)
Modulation Selection (Commercial)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
± 1.125
± 1.75
± 0.75
± 1.25
± 1.25
± 2.00
Reserved
Reserved
Modulation Rate (KHz)
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 20.83KHz
(FIN /40) * 20.83KHz
Reserved
Reserved
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 9
November 2006
rev 1.3
Spread Range Selection at 50MHz (Automotive)
MRA
0
0
0
0
1
1
1
1
P2040A
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
± 1.25
± 2.00
± 1.00
± 1.50
± 1.25
± 2.00
± 1.25
± 2.00
Modulation Rate
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
Spread Range Selection at 70MHz (Automotive)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
± 1.00
± 1.50
± 0.70
± 1.00
± 1.15
± 2.00
± 1.15
± 1.75
Modulation Rate
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 34.72KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
(F
IN
/40) * 20.83KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
November 2006
rev 1.3
Spread Spectrum Selection
P2040A
The
Modulation Selection Table
defines the possible spread spectrum options. The optimal setting should minimize system
EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1).
For example, P2040A is designed for high-resolution, flat panel applications and is able to support an XGA
(1024 x 768)
flat panel operating at 65MHz (F
IN
) clock speed. A spreading selection of MRA=0, SR1=1 and SR0=0 provides a percentage
deviation of ±0.75% from F
IN
. This results in the frequency on ModOUT being swept from 64.51MHz to 65.49MHz at a
modulation rate of 56.24KHz.
Refer Modulation Selection Table.
The example in the following illustration is a common EMI
reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile
graphic accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
+3.3V
65MHz from graphics accelerator
1 CLKIN
2 MRA
3 SR1
4 VSS
VDD
SR0
8
7
0.1µF
Modulated 65MHz signal with
±0.75 deviation and modulation
rate of 56.24KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of the
graphics accelerator.
ModOUT 6
SSON# 5
P2040A
Digital control for the SS enable
or disable
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
November 2006
rev 1.3
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
P2040A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
-40 to +125
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input low voltage
Parameter
Input high voltage
Input low current
(pull-up resistor on inputs SR0, SR1 and MRA)
Input high current (pull-down resistor on input SSON#)
Output low voltage (VDD = 3.3V, I
OL
= 20mA)
Output high voltage (VDD = 3.3V, I
OH
= 20mA)
Static supply current standby mode
Dynamic supply current (3.3V and 10pF loading)
Operating voltage
Power-up time (first locked cycle after power up)
Clock output impedance
Min
VSS - 0.3
2.0
-35
-
-
2.5
-
7
2.7
-
-
Typ
-
-
-
-
-
-
0.6
10
3.3
0.18
50
Max
0.8
VDD + 0.3
-
35
0.4
-
-
13
3.7
-
-
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
Parameter
Min
30
30
0.7
0.6
-
45
Typ
-
-
0.9
0.8
-
50
Max
100
100
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
京公网安备 11010802033920号
EEWORLD
