SED1570 Series
GENERAL DESCRIPTION
The SED1570 is an 80 output segment (column) driver
with an internal display RAM. This drive is suitable for
driving a dot matrix LCD panel; from a mid-range
capacity dot matrix LCD panel to a CGA class dot matrix
LCD panel. This device is used with the SED1635.
The display data is stored in the internal display RAM
and an LCD panel drive signal is generated. As a result,
this device allows configuration of an ultra low power
display system since the display data is not transferred
unless the display is changed.
In addition, the logic power is low voltage; a wide range
of applications is possible.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Display duty cycle: 1/64 – 1/200
LCD driver output: 80 out
Internal display RAM: 200
×
80 bits
Slim chip
Ultra low power consumption
Power
V
DD
– V
SS
2.7 V to 5.5 V
V
DD
– V
EE
8.0 V to 20 V
High speed and low power date transfer by the 4-bit
bus enables chain method
Non-bias display off function
Output shift direction-pin selection
Adjustable LCD power offset bias for V
DD
level
Package Chip
SED1570D
0A
(Al pad)
SED1570D
0B
(Au bump)
PAD DIMENSIONS
31
32
Y
1
99
X
49
D1570D
50
81
82
Chip Size
Pad Center Size
Pad Pitch
Chip Thickness
Bump Size
Pump Pitch
Chip Thickness
Bump Height
8.04 mm
×
3.51 mm
100
µm ×
100
µm
170
µm
(Min.)
400
µm ±25 µm
(Al Pad)
92
µm ×
82
µm
170
µm
(Min.)
525
µm
17~28
µm
(reference)
EPSON
9–1
SED1570 Series
PIN DESCRIPTION
Pin Name
X1 – X80
D
0
– D
3
XSCL
I/O
O
I
I
Function
LCD drive segment (column) output
The output changes with the LP’s trailing edge.
Display data input
Display data shift clock input
Reads the display data (D
0
– D
3
) into the data register with a trailing
edge.
Display data latch clock input
• The display RAM data (specified by the low address shift register) is read
into the latch with a leading edge, and the LCD display data is output.
• For a specified low address, the contents of the write register are written
in the display RAM. (At Data transfer mode)
• Resets the enable control circuit.
Enable I/O
• Configured by SHL.
• Output is reset to “H” by LP input. When the 80 bit display data is read,
the output falls to “L” automatically.
• To connect in cascade format, connect these pins to the next level EIO.
Shift direction and input/output select input
• If the display data is entered in the input (D
3
, D
2
, D
1
, D
0
) in the order of
(a1, a2, a3, a4) (b1, b2, b3, b4) … (t1, t2, t3, t4), the relationship of the
display data and the segment output is as given in the table below.
SHL
L
H
DOFF
I
Xn (SEG output)
EIO
80 79 78 77 76 75 … 6 5 4 3 2 1 1 2
a1 a2 a3 a4 b1 b2 … s3 s4 t1 t2 t3 t4 O I
t4 t3 t2 t1 s4 s3 … b2 b1 a4 a3 a2 a1 I O
1
No. of
Pins
80
4
1
LP
I/O
1
EIO1
EIO2
I/O
2
SHL
I
1
FR
YD
I
I
V
0
, V
2
,
V
3
, V
5
V
EE
V
DD
, V
SS
Power
supply
Power
supply
Power
supply
Forced blank input
In the “L” level, the segment output is forced to the V0 level.
The display RAM data is maintained.
LCD AC drive signal input
Scan start input
• Rests the low address counter decoder.
• The number of scanned lines (number of low addresses) for the
display RAM is determined by the number of LP pulses, which are
input in one YD cycle.
LCD drive power input
V
DD
≥
V
0
≥
V
2
≥
V
3
≥
V
5
≥
V
EE
LCD drive power input V
DD
– V
EE
Logic power input
V
DD
: connect to the system V
CC
pin.
V
SS
: connect to the system GND.
1
1
4
1
2
9–4
EPSON
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EEWORLD
