SDC-14610/15 SERIES
THREE CHANNEL 14- AND 16-BIT
TRACKING S/D CONVERTERS
FEATURES
DESCRIPTION
The SDC-14610/15 Series are small low
cost triple synchro- or resolver-to-digital
converters. The SDC-14610 Series is
fixed at 14 bits, the SDC-14615 at 16
bits. The three channels are indepen-
dent tracking types but share digital out-
put pins and a common reference.
The velocity output (VEL) from the
SDC-14610/15 Series, which can be
used to replace a tachometer, is a 4 V
signal referenced to ground with a lin-
earity of 1% of output voltage.
A BIT output is optional and is a logic
line that indicates LOS (Loss Of
Signal) or excessive converter error.
Due to pin limitations this option will
exclude the velocity output.
SDC-14610/15 Series conver t-
ers are available with operating
temperature ranges of 0°C to
+70°C and -55°C to +125°C, and
MIL-PRF-38534 processing is
available.
•
Fixed 14- or 16-Bit Resolution
•
Small Size 36-Pin DDIP Package
•
Three Independent Converters
•
Low Cost
•
Velocity Output Eliminates
Tachometer
APPLICATIONS
With its low cost, small size, high
accuracy, and versatile perfor-
mance, the SDC-14610/15 Series
converters are ideal for use in mod-
ern high-performance military and
industrial position control systems.
Typical applications include radar
antenna positioning, navigation and
fire control systems, motor control,
and robotics.
•
Optional BIT Output
•
High Reliability Single Chip
Monolithic
•
-55°C to +125°C Operating
Temperature Range
•
MIL-PRF-38534 Processing
Available
OPTIONAL
+REF
-REF
R
BIT
REFERENCE CONDITIONER
LOS
BIT
DETECTOR
ERROR
C
I
S1
S2
S3
S4
INPUT OPTION
CONTROL
TRANSFORMER
R
I
GAIN
DEMODULATOR
VEL
HYSTERESIS
INTEGRATOR
14/16-BIT
UP/DOWN
COUNTER
VCO & TIMING
DATA LATCH
8
EM DATA
EL
INH (Common)
FIGURE 1. SDC-14610/15 BLOCK DIAGRAM (ONE CHANNEL)
©
1991 ILC Data Device Corporation
TABLE 1. SDC-14610/15 SPECIFICATIONS (EACH CHANNEL)
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10% signal amplitude variation, and 10% har-
monic distortion.
Each Channel unless stated otherwise.
PARAMETER
UNIT
VALUE
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max Voltage No Damage
Input Impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Bits
Min
LSB
LSB
14
4 + 1 LSB
16
2(4) + 1 LSB
1 max
1 max
(+REF, -REF ),
Common to All Channels
differential
TABLE 1. SDC 14610/15 SPECIFICATIONS (CONTINUED)
PARAMETER
DIGITAL INPUT/OUTPUT
OUTPUTS
(continued)
Built-In-Test (BIT)(Optional)
UNIT
VALUE
Drive Capability
2 & 11.8 V UNITS
90 V unit
Vrms 2-35
10-130
Hz
360-5000
see note
Ohm 60k
Ohm 120k
Vpeak 50,
100 transient
270k min
540k min
200
300 transient
Logic 0 = BIT condition
±100 LSBs of error with a fil-
ter of 500 µs or LOS.
Each Channel
TTL 50 pF +
Logic 0; 1 TTL load, 1.6 mA
at 0.4 V max
Logic 1; 10 TTL loads, -0.4
mA at 2.8 V min
CMOS Logic 0; 100 mV max driving
Logic 1; +5 V supply minus
100 mV min driving
Device Type
60 Hz
4000 Hz
Hz
Hz
1/s
2
1/s
1/s
1/s
1/s
bits
rps
rps
deg/s
2
msec
47-5 k
15
830
0.17
5k
29
14.5
14
1.25
1
18
1100
16
0.31
0.25
4.5
2500
360-5 k
103
53k
1.33
40k
230
115
14
10
8
1160
140
16
2.5
2
290
320
DYNAMIC CHARACTERISTICS
Each Channel
Input Frequency
Bandwidth(Closed Loop)
Ka
A1
A2
A
B
Resolution
Tracking Rate
typical
minimum
Acceleration (1 LSB lag)
Settling Time (179° step max)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Voltage Scaling
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current (Ea.)
TEMPERATURE RANGE
Operating
-30X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
Each Channel
Ohm 123k
Ohm 80k
V
180 max
Ohm 52k
Ohm 34k
V
30 max
Each Channel
Positive for increasing angle
4.5 typ,4 min
10
10 typ
20 max
100 typ 200 max
1 typ
2 max
0.5 typ 1 max
5 typ
10 max
15 typ
30 max
20 max
1 typ
2 max
Total Device
+5
-5
5
10
+7
-7
36 typ, 51 max
Ohm 140k
Ohm 70k
V
30 max
Vrms 2 nom, 2.3 max
V
25 cont, 100 pk transient
Ohm 20 M//10 pF min
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µa max P.U. current
source to +5 V //5 pF max.
CMOS transient protected
Each Channel
Logic 0 inhibits; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
Common to All Channels
8 parallel lines; 2 bytes natural
binary angle, positive logic
±V
rps/FS
±%
ppm/°C
±%
±%
mV
µV/°C
kOhm
(Vp/V)%
V
±%
V
mA
Inhibit (lNH)(common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14(16) (EL)
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
Outputs
Parallel Data [1-14(16)]
in
(mm)
oz
1.70 x 0.78 x 0.21
(43.2 x 19.8 x 5.3)
0.66
bits
Note: 47 - 5k for 90 V, 60 Hz; 360 - 5k for 90 V, 400 Hz
2
THEORY OF OPERATION
The SDC-14610/15 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver-to-digital converter.
FIGURE 1 is the Functional Block Diagram of SDC-14610/15
Series. The converter operates with ±5 V dc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of three main sec-
tions; an input front-end, a converter, and a digital interface. The
converter front-end differs for synchro, resolver and direct inputs.
An electronic Scott-T is used for synchro inputs, a resolver con-
ditioner for resolver inputs and a sine and cosine voltage follow-
er for direct inputs. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 14-bit digital angle
φ.
Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ -
φ)
using
amplifiers, switches, logic and capacitors in precision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters ratioed capacitors
are used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above.
- Error Gradient = 0.011 volts per LSB (CT+Error Amp+Demod)
- Integrator gain =
- VCO Gain =
1 volts per second per volt
R
i
C
i
1
LSBs per second per volt
1.25 R
v
C
v
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14610/15 Series converters:
1) Power supplies are ±5 V dc. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
2) Direct inputs are referenced to A GND.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in six
bytes. The Enable MSB (EM A,EM B, or EM C) is used for the
most significant 8 bits and Enable LSB (EL A, EL B, or EL C) is
used for the least significant bits. As shown in FIGURE 4, output
data is valid 150 nanoseconds maximum after the application of
a low-going enable pulse. The tri-state data bus returns to the
high impedance state 100 nanoseconds maximum after the ris-
ing edge of the enable signal.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its functional block diagram and its bode plots (open and
closed loop); these are shown in FIGUREs 1 and 2 respectively.
The open loop transfer function is as follows:
GAIN = 4
OPEN LOOP
-1
2d
b/
oc
(CRITICALLY DAMPED)
2A
ω
(rad/sec)
10B
/oc
t
B
A
(B=A/2)
t
-6
db
- GAIN = 0.4
Open Loop Transfer Function =
S
(
B +1
)
S
(
S +1
10B
)
A
2
2
f
3db
= BW =
CLOSED LOOP
2A
2 2A
2 A (Hz)
π
ω
(rad/sec)
where A is the gain coefficient
and B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
FIGURE 2. BODE PLOTS
3
DOT
IDENTIFIES
PIN 1
INHIBIT
1.700 ±0.005
(43.2 ±0.13)
0.09 ±0.01
(2.3 ±0.25)
DATA
,,,,,,
500 ns MAX
DATA
VALID
0.775 ±0.005
(19.7 ±0.13)
BOTTOM VIEW
0.600 ±0.005
(15.2 ±0.13)
0.10 ±0.01
(2.5 ±0.3)
1.895 ±0.005
(48.1 ±0.13)
0.21 MAX
(5.3)
SEATING
PLANE
SIDE VIEW
0.086 TYP
RADIUS
FIGURE 3. INHIBIT TIMING
0.015 MAX
(0.39)
0.055 (1.4)
RAD TYP
0.25 MIN
(6.4)
0.100 TYP(2.54)
TOL. NON-
CUMULATIVE
0.018 (0.46)
DIAM TYP
ENABLE
DATA
HIGH Z
FIGURE 4. ENABLE TIMING
BIT, BUILT-IN-TEST (OPTIONAL)
,
150 ns MAX
DATA
VALID
,
100 ns MAX
HIGH Z
Notes:
1. Dimensions are in inches (millimeters).
2. Lead identification numbers are for reference only.
3. Lead clusters shall be centered within ±0.01 of outline dimensions. Lead spac-
ing dimensions apply only at seating plane.
4. Pin material meets solderability requirements to MIL-STD-202E, Method 208C.
5. Case is electrically floating.
FIGURE 5. SDC-14610/15 MECHANICAL OUTLINE
TABLE
S1A(R)
S2A(R)
S3A(R)
S4A(R)
(Ground)
S1B(R)
S2B(R)
2. PINOUTS
N.C.
+COSA(D)
+SINA(D)
N.C.
(36
36
36
34
PIN)*
VEL A (Velocity Output)**
EM A (Enable MSBs)
EL A (Enable LSBs)
This output is a logic line that will flag an internal fault condition,
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal error and, when it exceeds ±100 LSBs, will set the line
to a logic 0; this condition will occur during a large-step input and
will reset to a logic 1 after the converter settles out. (The error
voltage is filtered with a 500 µs filter) BIT will set for an overve-
locity condition because the converter loop can’t maintain
input/output sync. BIT will also be set if a total LOS (loss of all
signals) occurs.
1 S1A(S)
2 S2A(S)
3 S3A(S)
4 N.C.
5 GND
7
8
S1B(S)
S2B(S)
33 INH (Inhibit)
32 VEL B (Velocity Output)**
31 EM B (Enable MSBs)
6 A GND (Analog Ground)
N.C.
30 EL B (Enable LSBs)
+COSB(D) 29 Bit 8/Bit 16***
+SINB(D)
N.C.
28 Bit 7/Bit 15***
27 Bit 6/Bit 14
26 Bit 5/Bit 13
25 Bit 4/Bit 12
24 Bit 3/Bit 11
23
22
21
20
19
Bit 2/Bit 10
Bit 1/Bit 9
VEL C (Velocity Output)**
EL C (Enable LSBs)
EM C (Enable MSBs)
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° hangup” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver can not
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
9 S3B(S)
S3B(R)
10 N.C.
S4B(R)
11 -5 V (Power Supply)
12 +5 V (Power Supply)
13 S1C(S)
S1C(R)
14
15
16
17
18
N.C.
S2C(S)
S2C(R)
+COSC(D)
S3C(S)
S3C(R)
+SINC(D)
N.C.
S4C(R)
N.C.
-REF (-Reference Input)
+REF (+Reference Input)
Notes: * (S) = Synchro; (R) = Resolver; (D) = 2 V Resolver Direct
** Replaced with BIT - “T” option.
*** Note: SDC-14615 Series only
4
ORDERING INFORMATION
SD-1461XT-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
Blank = None of the Above
Accuracy:
2 = ±4 + 1 LSB
4 = ±2 minutes + 1 LSB (Not available with 14-bit units.)
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See table below.)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Output Option:
Blank = Standard Velocity Output (VEL)
T = Built-In-Test Output, instead of VEL
Input Option:
0 = 11.8 V, Synchro, 14 bit, 400 Hz
1 = 11.8 V, Resolver, 14 bit, 400 Hz
2 = 90 V, Synchro, 14 bit, 400 Hz
3 = 2 V, Direct, 14 bit, 400 Hz
4 = 90 V, Synchro, 14 bit, 60 Hz
5 = 11.8 V, Synchro, 16 bit, 400 Hz
6 = 11.8 V, Resolver, 16 bit, 400 Hz
7 = 90 V, Synchro, 16 bit, 400 Hz
8 = 2 V, Direct 16 bit, 400 Hz
9 = 90 V, Synchro, 16 bit, 60 Hz
*Standard DDC Processing with burn-in and full temperature test—see table below.
STANDARD DDC PROCESSING
MIL-STD-883
TEST
METHOD(S)
INSPECTION
SEAL
TEMPERATURE CYCLE
CONSTANT ACCELERATION
BURN-IN
2009, 2010, 2017, and 2032
1014
1010
2001
1015, Table 1
CONDITION(S)
—
A and C
C
A
—
5
MCU
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