A43E06161
Preliminary
Document Title
512K X 16 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
0.1
512K X 16 Bit X 2 Banks Synchronous DRAM
History
Initial issue
Modify t
SS
from 3ns to 2ns
Modify t
SH
from 1.5ns to 1ns
Modify I
CC6
from 0.5mA to 200μA
Issue Date
May 3, 2005
July 31, 2005
Remark
Preliminary
PRELIMINARY
(July, 2005, Version 0.1)
AMIC Technology, Corp.
A43E06161
Preliminary
Features
Low power supply
- VDD: 1.8V
- VDDQ: 1.8V
LVCMOS compatible with multiplexed address
Dual banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
Clock Frequency: 105MHz @ CL=3 (-95)
133MHz @ CL=3 (-75)
512K X 16 Bit X 2 Banks Synchronous DRAM
Industrial operating temperature range: -40ºC to +85ºC
for –U
Pb-Free type for -F
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
Available in 50-pin TSOP(II) package
General Description
The A43E06161 is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 524,288 words by 16
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies,
programmable latencies allows the same device to be useful
for a variety of high bandwidth, high performance memory
system applications.
Pin Configuration
TSOP (II)
NC/RFU
VDDQ
VDDQ
UDQM
VSSQ
DQ
13
DQ
12
DQ
11
DQ
10
VSSQ
DQ
15
DQ
14
CKE
VSS
DQ
9
DQ
8
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
A43E06161V
1
VDD
2
DQ
0
3
DQ
1
4
VSSQ
5
DQ
2
6
DQ
3
7
VDDQ
8
DQ
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DQ
7
CS
BA
A10/AP
CAS
RAS
LDQM
VSSQ
VDDQ
VDD
A0
A1
A2
DQ
5
DQ
6
WE
A3
PRELIMINARY
(July, 2005, Version 0.1)
1
AMIC Technology, Corp.
VSS
CLK
NC
A9
A8
A7
A6
A5
A4
A43E06161
Block Diagram
LWE
I/O Control
Data Input Register
Bank Select
LDQM
Row Buffer
Refresh Counter
Row Decoder
Output Buffer
Sense AMP
512K X 16
CLK
Address Register
512K X 16
DQi
LCBR
LRAS
Column Buffer
ADD
Column Decoder
Latency & Burst Length
LRAS
LCAS
LRAS
LCBR
LWE
LWCBR
Timing Register
Programming Register
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
PRELIMINARY
(July, 2005, Version 0.1)
2
AMIC Technology, Corp.
A43E06161
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A10/AP
Address
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BA
Bank Select Address
Selects band for read/write during column address latch time.
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
RAS
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +1.7V~1.95V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CAS
WE
L(U)DQM
DQ
0-15
VDD/VSS
VDDQ/VSSQ
NC/RFU
PRELIMINARY
(July, 2005, Version 0.1)
3
AMIC Technology, Corp.
A43E06161
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
°
C to +150
°
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Capacitance
CI1
CI2
A0 to A10, BA
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
UDQM, LDQM
DQ0 to DQ15
2.0
2.0
4.0
4.0
pF
pF
Data Input/Output Capacitance
CI/O
3.5
6.0
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, T
A
= -25ºC to +70ºC or -40ºC to +85ºC)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
DQ Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
VDD
VDDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
1.7
1.7
0.8 x VDDQ
-0.3
VDDQ-0.2
-
-1
-1.5
1.8
1.8
-
0
-
-
-
-
1.95
1.95
VDD+0.3
0.3
-
0.2
1
1.5
See Figure 1
V
V
V
V
V
V
µ
A
µ
A
Note 1
I
OH
= -0.1mA
I
OL
= 0.1mA
Note 2
Note 3
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
PRELIMINARY
(July, 2005, Version 0.1)
4
AMIC Technology, Corp.
京公网安备 11010802033920号
EEWORLD
