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A54SX08P-2PL208M

Description
FPGA, 1452 CLBS, 16000 GATES, 320 MHz, PQFP208
Categorysemiconductor    Programmable logic devices   
File Size363KB,57 Pages
ManufacturerETC
Download Datasheet Parametric View All

A54SX08P-2PL208M Overview

FPGA, 1452 CLBS, 16000 GATES, 320 MHz, PQFP208

A54SX08P-2PL208M Parametric

Parameter NameAttribute value
Number of terminals208
Minimum operating temperature-55 Cel
Maximum operating temperature125 Cel
Processing package descriptionPLASTIC, MO-143, QFP-208
each_compliYes
stateActive
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max320 MHz
The maximum delay of a CLB module0.7000 ns
jesd_30_codeS-PQFP-G208
jesd_609_codee0
moisture_sensitivity_level3
Number of configurable logic modules1452
Number of equivalent gate circuits16000
organize1452 CLBS, 16000 GATES
Packaging MaterialsPLASTIC/EPOXY
ckage_codeFQFP
packaging shapeSQUARE
Package SizeFLATPACK, FINE PITCH
eak_reflow_temperature__cel_225
qualification_statusCOMMERCIAL
seated_height_max4.1 mm
Rated supply voltage3.3 V
Minimum supply voltage3 V
Maximum supply voltage3.6 V
surface mountYES
CraftsmanshipCMOS
Temperature levelMILITARY
terminal coatingTIN LEAD
Terminal formGULL WING
Terminal spacing0.5000 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_30
length28 mm
width28 mm
dditional_featureCAN ALSO BE OPERATED AT 5V; 24000 SYSTEM GATES ALSO AVAILABLE
v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e
F ea t u r es
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
• 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• 0.35µ CMOS
S X P r od u c t P ro fi l e
A54SX08
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
8,000
12,000
768
512
256
130
3
Yes
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
144
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
176
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
144, 176
A54SX32
32,000
48,000
2,880
1800
1,080
249
3
Yes
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
208
144, 176
313, 329
June 2003
1
© 2003 Actel Corporation
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