DATA SHEET
GaAs INTEGRATED CIRCUIT
μ
PG2151TK
L, S-BAND SPDT SWITCH
DESCRIPTION
The
μ
PG2151TK is a GaAs MMIC for L, S-band SPDT (Single Pole Double Throw) switch which was developed for
mobile phone and another L, S-band application.
This device can operate 2 control switching by control voltage 1.8 to 5.3 V. This device can operate frequency from
0.5 to 3.0 GHz, having the low insertion loss and high isolation.
This device is housed in a 6-pin lead-less minimold (1511) package. And this package is able to high-density
surface mounting.
FEATURES
• Switch control voltage
•
: V
cont (H)
= 1.8 to 5.3 V (2.6 V TYP.)
: V
cont (L)
=
−0.2
to +0.2 V (0 V TYP.)
Low insertion loss
: L
INS
1 = 0.30 dB TYP. @ f = 0.5 to 1.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
: L
INS
2 = 0.35 dB TYP. @ f = 1.0 to 2.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
: L
INS
3 = 0.50 dB TYP. @ f = 2.0 to 3.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
High isolation
: ISL1 = 25 dB TYP. @ f = 0.5 to 1.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
: ISL2 = 18 dB TYP. @ f = 1.0 to 2.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
: ISL3 = 13 dB TYP. @ f = 2.0 to 3.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
Handling power
: P
in (0.1 dB)
= +21.0 dBm TYP. @ f = 2.0 GHz, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V
High-density surface mounting : 6-pin lead-less minimold package (1.5
×
1.1
×
0.55 mm)
•
•
•
APPLICATIONS
• L, S-band digital cellular or cordless telephone
TM
• W-LAN, WLL and Bluetooth etc.
ORDERING INFORMATION
Part Number
Order Number
Package
6-pin lead-less
minimold
(1511) (Pb-Free)
Note
Marking
G4N
Supplying Form
•
Embossed tape 8 mm wide
•
Pin 1, 6 face the perforation side of the tape
•
Qty 5 kpcs/reel
μ
PG2151TK-E2
μ
PG2151TK-E2-A
Note
With regards to terminal solder (the solder contains lead) plated products (conventionally plated), contact
your nearby sales office.
Remark
To order evaluation samples, contact your nearby sales office.
Part number for sample order:
μ
PG2151TK
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. PG10600EJ01V0DS (1st edition)
Date Published May 2006 NS CP(K)
Printed in Japan
2006
μ
PG2151TK
PIN CONNECTIONS AND INTERNAL BLOCK DIAGRAM
Pin No.
1
Pin Name
OUTPUT1
GND
OUTPUT2
V
cont
2
INPUT
V
cont
1
(Top View)
1
2
3
6
5
4
1
2
3
(Top View)
6
5
4
6
5
4
(Bottom View)
1
2
3
TRUTH TABLE
V
cont
1
Low
High
V
cont
2
High
Low
INPUT−OUTPUT1
OFF
ON
INPUT−OUTPUT2
ON
OFF
ABSOLUTE MAXIMUM RATINGS (T
A
= +25°C, unless otherwise specified)
Parameter
Switch Control Voltage
Input Power
Operating Ambient Temperature
Storage Temperature
Symbol
V
cont
P
in
T
A
T
stg
Ratings
+6.0
Note
Note
⎪V
cont
1
−
V
cont
2⎪
≤
6.0 V
RECOMMENDED OPERATING RANGE (T
A
= +25°C, unless otherwise specified)
Parameter
Switch Control Voltage (H)
Switch Control Voltage (L)
Symbol
V
cont (H)
V
cont (L)
MIN.
1.8
−0.2
TYP.
2.6
0
MAX.
5.3
+0.2
Unit
V
V
G4N
2
3
4
5
6
Unit
V
dBm
°C
°C
+26
−45
to +85
−55
to +150
2
Data Sheet PG10600EJ01V0DS
μ
PG2151TK
ELECTRICAL CHARACTERISTICS
(T
A
= +25°C, V
cont (H)
= 2.6 V, V
cont (L)
= 0 V, DC cut capacitors = 56 pF, unless otherwise specified)
Parameter
Insertion Loss 1
Insertion Loss 2
Insertion Loss 3
Isolation 1
Isolation 2
Isolation 3
Input Return Loss
Output Return Loss
0.1 dB Loss Compression
Input Power
Note
Symbol
L
INS
1
L
INS
2
L
INS
3
ISL1
ISL2
ISL3
RL
in
RL
out
P
in (0.1 dB)
Test Conditions
f = 0.5 to 1.0 GHz
f = 1.0 to 2.0 GHz
f = 2.0 to 3.0 GHz
f = 0.5 to 1.0 GHz
f = 1.0 to 2.0 GHz
f = 2.0 to 3.0 GHz
f = 0.5 to 3.0 GHz
f = 0.5 to 3.0 GHz
f = 2.0 GHz
MIN.
−
−
−
22
15
10
−
−
+18.0
−
TYP.
0.30
0.35
0.50
25
18
13
20
20
+21.0
MAX.
0.42
0.47
0.65
−
−
−
−
−
−
Unit
dB
dB
dB
dB
dBm
Switch Control Current
Switch Control Speed
I
cont
t
SW
50% CTL to 90/10% RF
0.2
1.0
20
−
μ
A
μ
s
−
Note
P
in (0.1 dB)
is measured the input power level when the insertion loss increases more 0.1 dB than that of linear
range.
Caution This device is used it is necessary to use DC cut capacitors.
The value of DC cut capacitors should be chosen to accommodate the frequency of operation,
bandwidth, switching speed and the condition with actual board of your system. The range of
recommended DC cut capacitor value is less than 100 pF.
Data Sheet PG10600EJ01V0DS
3
FPGA/CPLD
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