PRELIMINARY DATA SHEET
MICRONAS
MSP 34x5G
Multistandard
Sound Processor Family
Edition March 5, 2001
6251-480-3PD
MICRONAS
MSP 34x5G
Contents
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Section
1.
1.1.
1.2.
1.3.
2.
2.1.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
2.4.
2.5.
2.5.1.
2.5.2.
2.5.3.
2.6.
2.6.1.
2.6.2.
2.7.
2.8.
2.9.
2.10.
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.4.1.
3.1.4.2.
3.1.4.3.
3.1.4.4.
3.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
Title
PRELIMINARY DATA SHEET
Introduction
Features of the MSP 34x5G Family and Differences to MSPD
MSP 34x5G Version List
MSP 34x5G Versions and their Application Fields
Functional Description
Architecture of the MSP 34x5G Family
Sound IF Processing
Analog Sound IF Input
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
Manual Mode
Preprocessing for SCART and I
2
S Input Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
Automatic Volume Correction (AVC)
Loudspeaker Outputs
Quasi-Peak Detector
SCART Signal Routing
SCART DSP In and SCART Out Select
Stand-by Mode
I
2
S Bus Interface
ADR Bus Interface
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
Control Interface
I
2
C Bus Interface
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x5G I
2
C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I
2
C-Controlling
MSP 34x5G Programming Interface
User Registers Overview
Description of User Registers
STANDARD SELECT Register
Refresh of STANDARD SELECT Register
STANDARD RESULT Register
Write Registers on I
2
C Subaddress 10
hex
Read Registers on I
2
C Subaddress 11
hex
Write Registers on I
2
C Subaddress 12
hex
2
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Contents, continued
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Section
3.3.2.7.
3.4.
3.5.
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
3.5.6.
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.3.6.
4.6.3.7.
4.6.3.8.
4.6.3.9.
4.6.3.10.
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
6.
6.1.
6.2.
6.3.
6.3.1.
Title
Read Registers on I
2
C Subaddress 13
hex
Programming Tips
Examples of Minimum Initialization Codes
B/G-FM (A2 or NICAM)
BTSC-Stereo
BTSC-SAP with SAP at Loudspeaker Channel
FM-Stereo Radio
Automatic Standard Detection
Software Flow for Interrupt driven STATUS Check
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Description
Pin Configurations
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
General Recommended Operating Conditions
Analog Input and Output Recommendations
Recommendations for Analog Sound IF Input Signal
Crystal Recommendations
Characteristics
General Characteristics
Digital Inputs, Digital Outputs
Reset Input and Power-Up
I
2
C Bus Characteristics
I
2
S-Bus Characteristics
Analog Baseband Inputs and Outputs, AGNDC
Sound IF Input
Power Supply Rejection
Analog Performance
Sound Standard Dependent Characteristics
Appendix A: Overview of TV Sound Standards
NICAM 728
A2 Systems
BTSC-Sound System
Japanese FM Stereo System (EIA-J)
FM Satellite Sound
FM-Stereo Radio
Appendix B: Manual/Compatibility Mode
Demodulator Write and Read Registers for Manual/Compatibility Mode
DSP Write and Read Registers for Manual/Compatibility Mode
Manual/Compatibility Mode: Description of Demodulator Write Registers
Automatic Switching between NICAM and Analog Sound
Micronas
3
MSP 34x5G
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Section
6.3.1.1.
6.3.1.2.
6.3.2.
6.3.3.
6.3.4.
6.3.5.
6.3.6.
6.3.7.
6.4.
6.4.1.
6.4.2.
6.4.3.
6.4.4.
6.4.5.
6.4.6.
6.4.7.
6.5.
6.5.1.
6.5.2.
6.5.3.
6.5.4.
6.5.5.
6.5.6.
6.5.7.
6.6.
6.6.1.
6.6.2.
6.7.
6.7.1.
6.7.2.
6.8.
6.9.
7.
7.1.
7.2.
8.
9.
Title
PRELIMINARY DATA SHEET
Function in Automatic Sound Select Mode
Function in Manual Mode
A2 Threshold
Carrier-Mute Threshold
Register AD_CV
Register MODE_REG
FIR-Parameter, Registers FIR1 and FIR2
DCO-Registers
Manual/Compatibility Mode: Description of Demodulator Read Registers
NICAM Mode Control/Additional Data Bits Register
Additional Data Bits Register
CIB Bits Register
NICAM Error Rate Register
PLL_CAPS Readback Register
AGC_GAIN Readback Register
Automatic Search Function for FM-Carrier Detection in Satellite Mode
Manual/Compatibility Mode: Description of DSP Write Registers
Additional Channel Matrix Modes
Volume Modes of SCART1 Output
FM Fixed Deemphasis
FM Adaptive Deemphasis
NICAM Deemphasis
Identification Mode for A2 Stereo Systems
FM DC Notch
Manual/Compatibility Mode: Description of DSP Read Registers
Stereo Detection Register for A2 Stereo Systems
DC Level Register
Demodulator Source Channels in Manual Mode
Terrestric Sound Standards
SAT Sound Standards
Exclusions of Audio Baseband Features
Compatibility Restrictions to MSP 34x5D
Appendix D: Application Information
Phase Relationship of Analog Outputs
Application Circuit
Appendix E: MSP 34x5G Version History
Data Sheet History
License Notice:
“Dolby Pro Logic” is a trademark of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec-
tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
4
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
EIA-J. The MSP 34x5G has optimum stereo perfor-
mance without any adjustments.
All MSP 34xxG versions are pin compatible to the
MSP 34xxD. Only minor modifications are necessary
to adapt a MSP 34xxD controlling software to the
MSP 34xxG. The MSP 34x5G further simplifies con-
trolling software. Standard selection requires a single
I
2
C transmission only.
Note:
The MSP 34x5G version has reduced control
registers and less functional pins. The remaining regis-
ters are software-compatible to the MSP 34x0G. The
pinning is compatible to the MSP 34x0G.
The MSP 34x5G has built-in automatic functions: The
IC is able to detect the actual sound standard automat-
ically (Automatic Standard Detection). Furthermore,
pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/
stereo/bilingual; no I
2
C interaction is necessary (Auto-
matic Sound Selection).
The MSP 34x5G can handle very high FM deviations
even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
China.
The ICs are produced in submicron CMOS technology.
The MSP 34x5G is available in the following packages:
PSDIP64, PSDIP52, PMQFP44, PLQFP64, and
PQFP80.
Multistandard Sound Processor Family
Release Note: Revision bars indicate significant
changes to the previous edition. The hardware and
software description in this document is valid for
the MSP 34x5G version B8 and following versions.
1. Introduction
The MSP 34x5G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to pro-
cessed analog AF-out, is performed in a single chip.
Figure 1–1 shows a simplified functional block diagram
of the MSP 34x5G.
These TV sound processing ICs include versions for
processing the multichannel television sound (MTS)
signal conforming to the standard recommended by
the Broadcast Television Systems Committee (BTSC).
The DBX noise reduction, or alternatively, Micronas
Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM-Stereo-Radio
standard.
Current ICs have to perform adjustment procedures in
order to achieve good stereo separation for BTSC and
Sound IF1
ADC
De-
modulator
Pre-
processing
Loud-
speaker
Sound
Processing
DAC
Loud-
speaker
I
2
S1
I
2
S2
Prescale
Source Select
I
2
S
SCART1
DAC
SCART
DSP
Input
Select
SCART2
ADC
Prescale
SCART
Output
Select
SCART1
MONO
Fig. 1–1:
Simplified functional block diagram of MSP 34x5G
Micronas
5
Microcontroller MCU
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