U1AFS600-FGG256 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> U1AFS600-FGG256

U1AFS600-FGG256: DescriptionIC,FPGA,13824-CELL,CMOS,BGA,256PIN,PLASTIC; CategoryProgrammable logic devices Programmable logic; File Size538KB，17 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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U1AFS600-FGG256 Overview

IC,FPGA,13824-CELL,CMOS,BGA,256PIN,PLASTIC

U1AFS600-FGG256 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	1 MM PITCH, GREEN, FBGA-256
Reach Compliance Code	compli
maximum clock frequency	350 MHz
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	13824
Equivalent number of gates	600000
Number of entries	119
Number of logical units	13824
Output times	119
Number of terminals	256
Maximum operating temperature	85 °C
Minimum operating temperature
organize	13824 CLBS, 600000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.5,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.68 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	17 mm

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Preliminary v0.4

Actel Fusion Mixed-Signal FPGAs

for the MicroBlade Advanced Mezzanine Card Solution

Features and Benefits

• Targeted to Advanced Mezzanine Card (AdvancedMC™)

Designs

• Designed in Partnership with MicroBlade

• 8051-Based Module Management Controller (MMC)

• Fully Compliant with PICMG AMC.0.R2.0 and IPMI v2.0

Specifications

• AdvancedMC Reference Design and Starter Kit

• Crystal Oscillator Support (32 kHz to 20 MHz)

• Programmable Real-Time Counter (RTC)

• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Low Power Consumption

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low Power Modes

High-Performance Reprogrammable Flash

Technology

•

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Nonvolatile, Retains Program when Powered Off

Live at Power-Up (LAPU) Single-Chip Solution

350 MHz System Performance

In-System Programming (ISP) and Security

• Secure ISP with 128-Bit AES via JTAG

• FlashLock

to Secure FPGA Contents

Advanced Digital I/O

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

– Built-In I/O Registers

– 700 Mbps DDR Operation

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down Resistor

• Pin-Compatible Packages across the Fusion Family

Embedded Flash Memory

• User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

• 1 kbit of Additional FlashROM

Integrated A/D Converter (ADC) and Analog I/O

•

Up to 12-Bit Resolution and up to 600 ksps

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High-Voltage Input Tolerance: –10.5 V to +12 V

Current Monitor and Temperature Monitor Blocks

Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths

• ADC Accuracy is Better than 1%

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

On-Chip Clocking Support

• Internal 100 MHz RC Oscillator (accurate to 1%)

MicroBlade Fusion Solutions

Fusion Devices

System Gates

Tiles (D-flip-flops)

General Information

Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

Memory

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Analog and I/Os

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

Notes:

1. Refer to the

CoreMP7

datasheet for more information.

2. Refer to the

Cortex-M1

product brief for more information.

U1AFS25

250,000

6,144

Yes

114

U1AFS600

600,000

13,824

Yes

108

172

U1AFS1500

1,500,000

38,400

Yes

270

252

October 2008

1 – Fusion Device Family Overview

Introduction

The Actel

MicroBlade-based

Fusion

mixed-signal FPGA satisfies the demand from system

architects for a device that simplifies design and unleashes their creativity. As the world’s first

mixed-signal programmable logic family,

MicroBlade-based

Fusion integrates mixed-signal

analog, flash memory, and FPGA fabric in a monolithic device. Actel

MicroBlade-based

Fusion

devices enable designers to quickly move from concept to completed design and then deliver

feature-rich systems to market. This new technology takes advantage of the unique properties of

Actel flash-based FPGAs, including a high-isolation, triple-well process and the ability to support

high-voltage transistors to meet the demanding requirements of mixed-signal system design.

Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many application

areas, including power management, smart battery charging, clock generation and management,

and motor control. Until now, these applications have only been implemented with costly and

space-consuming discrete analog components or mixed-signal ASIC solutions. Actel Fusion mixed-

signal FPGAs present new capabilities for system development by allowing designers to integrate a

wide range of functionality into a single device, while at the same time offering the flexibility of

upgrades late in the manufacturing process or after the device is in the field. Actel Fusion devices

provide an excellent alternative to costly and time-consuming mixed-signal ASIC designs. In

addition, when used in conjunction with the Actel

for the MicroTCA market.

Actel Fusion

technology represents the definitive mixed-signal FPGA platform.

Flash-based Fusion devices are live at power-up. As soon as system power is applied and within

normal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-

based lock and industry-leading AES decryption, used to secure programmed intellectual property

(IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analog

and digital programmable logic solution available today.

To support this new ground-breaking technology, Actel has developed a series of major tool

innovations to help maximize designer productivity. Implemented as extensions to the popular

Actel Libero

Integrated Design Environment (IDE), these new tools allow designers to easily

instantiate and configure peripherals within a design, establish links between peripherals, create

or import building blocks or reference designs, and perform hardware verification. This tool suite

will also add comprehensive hardware/software debug capability as well as a suite of utilities to

simplify development of embedded soft-processor-based solutions.

MicroBlade-based Fusion (U1AFS) devices are targeted to Actel’s Advanced Mezzanine Card (AMC)

design developed in partnership with MicroBlade, Inc. The AMC design is an 8051-based Module

Management Controller (MMC) and is fully compliant with the PICMG Advanced Mezzanine Card

AMC.0 R2.0 and IPMI v2.0 specification, implementing in the AMC reference design and AMC

Starter Kit as a complete board including a variable load board 100 W payload. The AMC reference

design is available for free download from the Actel website, including board design files,

documentation, FPGA design as a complete Libero

Integrated Design Environment (IDE) project,

and an executable firmware image. The AMC Starter Kit adds complete firmware source code in C

format. Designs based on the AMC Starter Kit (part number UTCA-AMC-SK) design are required to

use one of the U1AFS devices: U1AFS250, U1AFS600, or U1AFS1500.

Pr e li m i n a ry v0 . 4

1-1

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