MP8060
16V, 3.5A Quad Channel Power Half-Bridge
The Future of Analog IC Technology
DESCRIPTION
The MP8060 is a
configurable dual channel full-
bridge
or quad channel half-bridge used as the
output stage of a Class-D audio amplifier. Each
full-bridge can be driven independently as
stereo single ended audio amplifiers or driven
complementary in a bridge tied load (BTL)
audio amplifier configuration.
The MP8060 features a low current shutdown
mode, standby mode, input under voltage
protection, thermal shutdown and fault flag
signal output. All channels of drivers interface
with standard logic signals.
The MP8060 is available in a 32 lead QFN 5X5
package.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
3.5A Peak Current Output
Up to 600KHz Switching Frequency
Integrated Power 0.4Ω Switches
30ns Switch Dead Time
All Switches have Over-Current Protection
Internal Under Voltage Protection
Internal Thermal Protection
2.6mA Operating Current
Fault Output Flag
Single Ended: 4W/Channel at 16V, 8Ω Load
Bridge Tied Load Output Power:
16W/Channel at 16V, 8Ω Load
Class D Audio Drivers
Motor Drivers
APPLICATIONS
•
•
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VDD
1N4148
D1
C1
1000uF
C2
1uF
L1
C3
0.1uF
C6
0.1uF
L2
1N4148
D3
CN1
C4
0.47uF
D2
10uH
OUT1A
C5
1uF
BST1A
PGND1A
SW1A
SW1A
VSP1
VSP1
SW1B
SW1B
OUT1B
C7
0.47uF
PWM1A
PWM1B
FAULT
SHDN
PWM2A
STBY
PWM2B
PWM1A
PWM1B
SHDNB
AGND
PWM2A
STBYB
PWM2B
PGND1B
BST1B
VDR1
D4
C8
0.1uF
10uH
FAULTB
MP8060
PGND2B
SW2B
SW2B
VSP2
VSP2
SW2A
SW2A
AGND
VDR2
BST2A
PGND2A
N/C
1N4148
C9
0.1uF
L3
CN2
C11
0.47uF
C12
1uF
BST2B
C10
0.1uF
D5
D6
10uH
OUT2A
1N4148
VDD
C13
1000uF
C14
1uF
D7
C15
0.1uF
D8
L4
10uH
C16
0.47uF
OUT2B
M8060 Rev. 0.9
5/5/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
1
16V, 3.5A QUAD CHANNEL POWER HALF-BRIDGE
ORDERING INFORMATION
Part Number*
MP8060EU
Package
QFN 5x5 – 32L
Top Marking
MP8060EU
Free Air Temperature (T
A
)
-20°C to +85°C
*For
Tape & Reel, add suffix –Z (e.g. MP8060EU–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP8060EU–LF–Z).
PACKAGE REFERENCE
PGND1B
PGND2A
26
BST1B
BST2A
VDR1
AGND
VDR2
NC
25
32
31
30
29
28
27
SW1B
SW1B
VSP1
VSP1
SW1A
SW1A
PGND1A
BST1A
1
2
3
4
5
6
7
8
PWM1B 10
SHDNB 12
AGND 13
14
STBYB 15
FAULTB 11
PWM2B 16
9
24
23
22
21
SW2A
SW2A
VSP2
VSP2
20 SW2B
19 SW2B
18
17
PGND2B
BST2B
PWM1A
PWM2A
ABSOLUTE MAXIMUM RATINGS
(1)
VSP Supply Voltage ................................. 18.5V
SW1/2 Pin Voltage............... -0.3V to V
SP
+ 0.3V
SW1/2 to BST1/2 ............................-0.3V to +6V
Voltage at All Other Pins.................-0.3V to +6V
Continuous Power Dissipation
(T
A
= +25°C)
(2)
............................................................. 3.5W
Storage Temperature............... -55°C to +150°C
Junction Temperature................................150°C
Lead Temperature ....................................260°C
Thermal Resistance
(4)
QFN32 (5x5) ...........................36 ....... 8 ....
°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of
the maximum junction temperature T
J
(MAX), the junction-to-
ambient thermal resistance
θ
JA
, and the ambient temperature
T
A
. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by P
D
(MAX) = (T
J
(MAX)-T
A
)/θ
JA
. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
θ
JA
θ
JC
Recommended Operating Conditions
(3)
VSP Supply Voltage ........................4.5V to 16V
Peak Output Current ...................3.5A Maximum
Operating Junct. Temp (T
J
)...... -20°C to +125°C
M8060 Rev. 0.9
5/5/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
2
16V, 3.5A QUAD CHANNEL POWER HALF-BRIDGE
ELECTRICAL CHARACTERISTICS
V
SP
= 12V, V
SHDNB
= 5V, T
A
= +25°C, unless otherwise specified.
Parameters
VSP Operating Current
VSP Shutdown Current
Operating VSP Threshold Low
Operating VSP Threshold High
STBYB Threshold Low
STBYB Threshold High
PWM Input Bias Current
SHDNB Threshold Low
SHDNB Threshold High
PWM1,2 Threshold Low
PWM1,2 Threshold High
SW1/2 On Resistance
SW1/2 Current Limit
(5)
SW1/2 Switching Frequency
SW1/2 Maximum Duty Cycle
(6)
SW1/2 Rise/Fall Time
PWM Pulse Width
Dead Time
(5)
PWM1,2 to SW1,2 Delay Time
Rising
PWM1,2 to SW1,2 Delay Time
Falling
Thermal Shutdown Temperature
(5)
V
SP
= 7.5V, High-Side and Low-
Side
V
PWM
= 0V, Sinking
V
PWM
= 5V, Sourcing
V
PWM
= 0 to 5V, 50% Duty Cycle
V
SP
= 7.5V, V
PWM
= 5V,
C
BST
= 100nF, f
SW
= 3.3kHz
V
PWM
= 0V to 5V
V
PWM
= 0V to 5V, High or Low
Pulse
I
OUT
= ±100mA
V
PWM
= 0V to 5V
V
PWM
= 5V to 0V
T
J
Rising, Hysteresis = 20°C
0.8
Symbol Condition
I
LOAD
= 0A，PWM1,2=0
V
SHDNB
= 0V
Min
Typ
2.6
2.5
3.8
4.0
1.1
1.9
0.1
1.1
1.9
1.4
1.8
0.4
3.5
3.5
0.6
99.5
10
40
30
35
35
150
2.2
1.0
2.2
2.2
Max
5
10
Units
mA
µA
V
V
V
V
µA
V
V
V
V
Ω
A
A
MHz
%
ns
ns
ns
ns
ns
°C
0.8
0.9
Notes:
5) Not production tested.
6) OUT drives low for 1.5µs every 300µs to charge the BST to SW capacitor.
M8060 Rev. 0.9
5/5/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
3
16V, 3.5A QUAD CHANNEL POWER HALF-BRIDGE
PIN FUNCTIONS
Pin #
1,2
3, 4
5,6
7
8
9
Name
SW1B
VSP1
SW1A
PGND1A
BST1A
PWM1A
Description
Switched Output 1B. Connect the output LC filter to SW1B. SW1B is valid approximately
100µs after VSP goes high.
Power Supply Input. Connect VSP1 to the positive side of the input power supply. Bypass
VSP1 to PGND as close to the IC as possible.
Switched Output 1A. Connect the output LC filter to SW1A. SW1A is valid approximately
100µs after VSP goes high.
Power Ground of Channel 1A. Connect the exposed pad on bottom side to the ground
plane.
Bootstrap Supply. BST1A powers the high-side gate of the SW1A stage. Connect a 0.1μF
or greater capacitor between BST1A and SW1A.
Driver Logic Input 1A. Drive PWM1A with the signal that controls the MP8060 SW1A.
Drive PWM1A high to turn on the high side switch; drive PWM1A low to turn on the
low-side switch.
Driver Logic Input 1B. Drive PWM1B with the signal that controls the MP8060 SW1B.
Drive PWM1B high to turn on the high side switch; drive PWM1B low to turn on the
low-side switch.
Fault Output. A low output at
FAULTB
indicates that the MP8060 has detected an over
temperature or over current condition. This output is open drain.
Shutdown Input. When low, the IC will be shut off.
Analog Ground.
Driver Logic Input 2A. Drive PWM2A with the signal that controls the MP8060 SW2A.
Drive PWM2A high to turn on the high side switch; drive PWM2A low to turn on the
low-side switch
Standby Input. Default low (internal pull-down). If driven high, the output of the drivers is
determined by the PWM1A/1B/2A/2B. If driven low, the output of both drivers is high
impedance.
Driver Logic Input 2B. Drive PWM2B with the signal that controls the MP8060 SW2B.
Drive PWM2B high to turn on the high side switch; drive PWM2B low to turn on the
low-side switch
Bootstrap Supply. BST2B powers the high-side gate of the SW2B stage. Connect a 0.1μF
or greater capacitor between BST2B and SW2B.
Power Ground of Channel 2B. Connect the exposed pad on the bottom side to the ground
plane.
Switched Output 2B. Connect the output LC filter to SW2B. SW2B is valid approximately
100µs after VSP goes high.
Power Supply Input. Connect VSP2 to the positive side of the input power supply. Bypass
VSP2 to PGND as close to the IC as possible.
Switched Output 2A. Connect the output LC filter to SW1A. SW1A is valid approximately
100µs after VSP goes high.
No connect.
Power Ground of Channel 2A. Connect the exposed pad on the bottom side to the ground
plane.
Bootstrap Supply. BST2A powers the high-side gate of the SW2A stage. Connect a 0.1μF
or greater capacitor between BST2A and SW2A.
10
11
12
13,29
14
PWM1B
FAULTB
SHDNB
AGND
PWM2A
15
STBYB
16
17
18
19,20
21, 22
23, 24
25
26
27
PWM2B
BST2B
PGND2B
SW2B
VSP2
SW2A
NC
PGND2A
BST2A
M8060 Rev. 0.9
5/5/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
4
16V, 3.5A QUAD CHANNEL POWER HALF-BRIDGE
PIN FUNCTIONS
(continued)
Pin #
28
Description
Gate Drive Supply Bypass. The voltage at VDR2 is supplied from an internal regulator from
VDR2 its respective VSP. VDR2 powers the internal circuitry and internal MOSFET gate drive for
SW2A and SW2B stage. Bypass VDR2 to AGND with a 0.1μF to 10μF capacitor.
Gate Drive Supply Bypass. The voltage at VDR1 is supplied from an internal regulator from
VDR1 its respective VSP. VDR1 powers the internal circuitry and internal MOSFET gate drive for
SW1A and SW1B stage. Bypass VDR1 to AGND with a 0.1μF to 10μF capacitor.
Bootstrap Supply. BST1B powers the high-side gate of the SW1B stage. Connect a 0.1μF
BST1B
or greater capacitor between BST1B and SW1B.
Power Ground of Channel 1B. Connect the exposed pad on the bottom side to the ground
PGND1B
plane.
Name
30
31
32
M8060 Rev. 0.9
5/5/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
5
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