EP3500TPDC-50.000M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Aug 28, 2020)
191 SVHC
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)
50.000MHz ±100ppm -20°C to +70°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Pin 1 Input Voltage (Vih and Vil)
Standby Current
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
50.000MHz
±100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating
Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25 °C, Shock, and Vibration)
±5ppm/year Maximum
-20°C to +70°C
5.0Vdc ±10%
45mA Maximum (Unloaded)
Vdd-0.4Vdc Minimum (IOH = -16mA)
0.4Vdc Maximum (IOL = +16mA)
4nSec Maximum (Measured at 20% to 80% of waveform)
50 ±5(%) (Measured at 1.4Vdc with TTL Load or at 50% of waveform with HCMOS Load)
50pF HCMOS Load Maximum
CMOS
Power Down (Disabled Output: Logic Low)
+2.0Vdc Minimum to enable output, +0.8Vdc Maximum to disable output, No Connect to enable output.
50µA Maximum (Pin 1 = Ground)
±100pSec Maximum, ±50pSec Typical
±30pSec Maximum
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, MEthod 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision G 02/27/2015 | Page 1 of 5
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EP3500TPDC-50.000M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
Power Down (Logic Low)
Ground/Case Ground
Output
Supply Voltage
3.20
±0.20
MARKING
ORIENTATION
2
1.30
MAX
2
2.54
±0.15
1
1.20 ±0.20
1.00 ±0.20 (x4)
3
3
4
LINE MARKING
1
E50.000
E=Ecliptek Designator
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
5.00
±0.20
4
1.20
±0.20 (x4)
2
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.20 (X4)
1.40 (X4)
1.14
Solder Land
(X4)
1.00
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Revision G 02/27/2015 | Page 2 of 5
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EP3500TPDC-50.000M
OUTPUT WAVEFORM & TIMING DIAGRAM
POWER DOWN INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% or 2.0V
DC
50% or 1.4V
DC
20% or 0.8V
DC
V
OL
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
OUTPUT DISABLE
(LOGIC LOW)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision G 02/27/2015 | Page 3 of 5
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EP3500TPDC-50.000M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low input capacitance (<12pF), 10X Attentuation Factor, High Impedance (>10Mohms), and
High bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. See applicable specification sheet
for ‘Load Drive Capability’.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision G 02/27/2015 | Page 4 of 5
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EP3500TPDC-50.000M
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
R
L
Value
(Ohms)
390
780
C
L
Value
(pF)
15
15
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
Power Down
or Tri-State
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision G 02/27/2015 | Page 5 of 5
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
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